Visit Extreme DA at the 45th Design Automation Conference: Discover Sign-off with Certainty and Enter to Win a 32GB Apple iTouch

Design Automation Conference 2008
Booth 1364

SANTA CLARA, Calif.--( BUSINESS WIRE)--In booth 1364 at the 45th Design Automation Conference (DAC), Extreme DA will exhibit the newest version of its next-generation timing sign-off solution, GoldTime, now with multi-dimensional optimization (MXO). The fast-growing company is the emerging leader in next-generation timing analysis software that improves the performance and yield of nanometer integrated circuits (ICs) with unmatched speed and analysis capacity and addresses process variations in semiconductor designs.

Extreme DA in Booth 1364

  • Extreme DA will provide informal demonstrations of the newest version of GoldTime, which now includes Extremes new MXO technology that delivers tape-out success across operational modes and corners and is 5X faster than traditional tools such as Synopsys PrimeTime.
  • Exhibit visitors can complete a brief survey to share with Extreme DA their opinions on crucial IC design issues.
  • Everyone who views a presentation or completes a survey will automatically be entered to win a 32GB Apple iTouch.
  • Extreme DA technologists will be on hand to talk with attendees about IC designs and how to achieve faster timing sign-off.

Extreme DA in Suite 1364

  • Extreme DA will host private meetings in its suites to demonstrate the new features and benefits of GoldTime and share its technology roadmap.
  • Suite presentations will include:

GoldTime Timing Analysis The New Standard in Sign-off Timing

Whats 5X faster than PrimeTime and uses less memory? What enables true multi-mode, multi-corner reporting and data consolidation in a single session? Which tool provides leading-edge IDMs with a distinct time to market advantage? Extreme DA has the answers in GoldTime timing analysis. Discover how GoldTime transforms your existing design closure and sign-off timing flows to new standards of capacity and performance.

ROAD The Path to Transistor-level Statistical Optimization

ROAD statistical optimization at the transistor level is a new generation tool that goes beyond statistical analysis. Targeted toward standard cell, memory, and mixed-signal designers, ROAD out-performs traditional Monte Carlo analysis by 10X or more, allowing for the first time ever, a practical statistical optimization flow. Get the details on why 45nm design teams world-wide have adopted ROAD.

Statistical STA The Time Is Now (Tutorial)

No longer a future concern, process variation and timing uncertainty are here at 45nm. Refresh what youve heard, but perhaps ignored, in the last two years regarding local and global variation and its impact on design performance and yield. Discover how Extreme DA solutions have found problems missed by corner-based analysis.

  • Prospective Extreme DA customers and partners may schedule suite presentations with Extreme DA executives and technologists in the suite by registering at
  • Editors and analysts may set up briefings with Extreme DA executives and technologists, by contacting Jean Armstrong, Armstrong Kendall, Inc., at 503-672-4680 or Email Contact.

About Extreme DA

Headquartered in Santa Clara, Calif., venture-funded Extreme DA develops and licenses software products that provide sign-off analysis and improve the performance and yield of nanometer integrated circuits prior to manufacture. The companys investors include Foundation Capital, IT-Farm Corporation, and Lanza techVentures. For the latest news and information on Extreme DA, visit or write to Email Contact.

Extreme DA, the Extreme DA logo, and Extreme DA GoldTime, MXO, and ROAD are trademarks of Extreme DA. All other legal marks are the property of their respective owners.


Armstrong Kendall, Inc.
PR Counsel for Extreme DA
Jean Armstrong, 503-672-4680
Email Contact

Review Article Be the first to review this article
Aldec Webinar Nov 30

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Computer History Museum: the Future of War is Here
More Editorial  
ASIC Design Engineer for Infinera Corp at Sunnyvale, CA
Senior SW Developer for EDA Careers at San Jose, CA
Senior PIC Test Development Engineer for Infinera Corp at Sunnyvale, CA
REVISED***Director Product Line RF/IC for EDA Careers at San Jose, CA
Principal PIC Hardware Controls Engineer for Infinera Corp at Sunnyvale, CA
Upcoming Events
“Empowering Leadership with WIT and WISDOM” at SEMI 673 South Milpitas Blvd. Milpitas CA - Nov 28, 2017
Artificial Intelligence and Convolution Neural Networks Discussion at San Jose State University Student Union Theater San Jose CA - Dec 4, 2017
Silicon Valley's Only Comprehensive Embedded Systems Conference at San Jose Convention Center 150 W. San Carlos St. San Jose CA - Dec 5 - 7, 2017
Oski Technology’s Decoding Formal Club Meeting at The Conference Center San Jose CA - Dec 7, 2017

Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise