Solido Design to Present Seminar at DATE Exploring Variation Robustness for Analog, Custom Digital and Memory Design

SANTA CLARA, Calif.—(BUSINESS WIRE)—March 5, 2008— Solido Design Automation, innovator of process variation solutions for transistor-level designers of analog/mixed-signal, custom digital and memory integrated circuits, today announced that the company will present a technical seminar on "Variation Robustness for Analog/Mixed-Signal, Custom Digital and Memory Design" at the Design Automation and Test Europe (DATE) Conference being held on March 10 - 14, 2008 at the ICM in Munich, Germany.
WHO:     Patrick Drennan, Chief Technology Officer, Solido Design
          Automation

WHAT:    This seminar will include a review of the physical phenomena
          and industry standard device models for variation sources,
          including random local and global variations and systematic
          proximity effects. New techniques to accelerate, increase
          accuracy and derive more information from statistical
          variation analysis will also be presented.

WHERE:   2008 DATE Conference, Munich, Germany
         At the ICM in room 2156

WHEN:    9:00 a.m. - 10:00 a.m. CET, March 12th
         Continental breakfast will be served


To register go to: http://www.solidodesign.com/date08_tech_seminar.shtml

About Solido Design Automation

Solido Design Automation Inc. provides process variation solutions for transistor-level designers of analog/mixed-signal, custom digital, and memory integrated circuits. The privately held company is venture capital funded and has offices in U.S.A., Canada, Japan and Europe. For further information, visit www.solidodesign.com or call 306-382-4100.

Contact:

PR for Solido Design Automation:
Michelle Clancy, 252-940-0981
Email Contact


Rating:


Review Article Be the first to review this article
CST: Webinar October 19, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
FPGA Engineer for Teradyne Inc at San Jose, CA
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
Preparing for the Cognitive Era: Education, Occupation and You at SJSU Student Union Theater 211 South 9th Street San Jose CA - Oct 18, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
15th IEEE/ACM ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise