Accellera Supports Interoperability, Attends Magma's MUSIC User's Summit

SANTA CLARA, CA -- (MARKET WIRE) -- Feb 21, 2008 --


Who

Accellera, the electronics industry organization focused on Electronic Design Automation (EDA) standards, is attending Magma Design Automation's MUSIC (Magma Users Summit on Integrated Circuits) event to support standards that facilitate electronic design tools interoperability and increase electronic design productivity. The Accellera exhibit will feature information about the organization's low power standard, Unified Power Format (UPF).

When and Where

5-7pm, Thursday, February 28, 2008

Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, CA 95054

Exhibit Hall D

Information

For more information about Accellera and Accellera standards, please visit www.accellera.org. To register for MUSIC, please visit www.magma-da.com/MUSIC.

About Accellera

Accellera provides design and verification standards for quick availability and use in the electronics industry. The organization and its members cooperatively deliver much-needed EDA standards that lower the cost of designing commercial IC and EDA products. As a result of Accellera's partnership with the IEEE, Accellera standards are provided to the IEEE standards body for formalization and ongoing change control. For more information about Accellera, please visit www.accellera.org.

All trademarks and tradenames are the property of their respective owners.

Add to Digg Bookmark with del.icio.us Add to Newsvine

Press Contact:
Georgia Marszalek
ValleyPR for Accellera
+ (650) 345-7477

Email Contact



Rating:


Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Blue Pearl: Best kept Secret in EDA
More Editorial  
Jobs
Field Application Engineer for Teradyne Inc at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Upcoming Events
CODES+ISSS 2017, Oct 15-20, 2017, Lotte Hotel, Seoul, South Korea at Lotte Hotel Seoul Korea (North) - Oct 15 - 20, 2017
DVCon 2017 Europe, Oct 16 - 17, 2017, Munich, Germany at Holiday Inn Munich City Centre Munich Germany - Oct 16 - 17, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise