Aldec Enhances Active-HDL with Multi-Design Hierarchical Workspaces

Designers can now Integrate Various Projects Into A Single, Top-Level Design


Henderson Nevada, September 30, 2002 -- Aldec, Inc., a pioneer in mixed language simulation and advanced design tools for FPGA and ASIC devices, today announced its Multi-Design Workspace feature present in Active-HDL’s new version 5.2; the Multi-Design Workspace feature is included in all configurations of Active-HDL for no additional cost. As designs become larger to meet the latest demands in technology, it is common design practice to split the entire system into smaller modules and assign each module to a different engineer in the team. Multi-Design Workspace allows each module to be created and tested in Active-HDL as a separate design and then shared with the rest of the team. Design managers can integrate all modules and use Active-HDL’s integrated source control interfaces to track and manage the changes from the different designers.

Increased Productivity
The Multi-Design Workspace feature is ideal for designers who are working on multiple design projects as well as design team managers, who can pool all of the designs’ resources and treat the discrete designs as one comprehensive unit. All modules can be designed separately and then integrated together as one top-level design.

Design Autonomy
The Workspace itself contains the source files and output files with simulation results. Even though a single workspace can consist of several designs, each discrete design maintains its own setting and attributes, such as synthesis and implementation tool mapping. Individual designers lose none of their preference settings or risk having their designs reverse-engineered through the Workspace function.

Support for Network Directories
The Multi-Design Workspace feature is the optimal way to manage a collection of design projects. The Workspace function adopts a UNC (Universal Naming Convention), allowing users to attach files or designs located anywhere on the local network to the appropriate workspace.

Design File Protection
In order to ensure that a design is not modified in error, only one design can be set as active at any given time. If an active design requires the same files or resources that are present in an inactive design, files can be dragged from an inactive design and are automatically copied and attached to the active design for its use as well.

Global Library Management
Multi-Design Workspace also allows the user to better mange all libraries of the workspace. Using this new feature, all libraries are treated as global until a design is opened, making those libraries associated with the active design a local library. Multi-Design Workspace acts like a universal library manager and simplifies design creation.

Availability
Multi-Design Workspace is included in all Active-HDL 5.2 configurations. Active-HDL 5.2 is available now and can be ascribed to either a floating or node-lock license for no additional cost. Active-HDL 5.2 includes Multi-Design Workspace, HDL Editor, State Machine Editor, and Block Diagram & Schematic Editors, Automatic Testbench Generation, Waveform Viewer/Editor, and a choice of VHDL, Verilog or mixed VHDL/Verilog/EDIF simulation. All sales include one year of product maintenance. To receive your FREE evaluation copy, contact Aldec at www.aldec.com.


About Aldec
Aldec, Inc., an 18-year EDA tool provider, is committed to delivering high-performance, HDL-based design verification software for UNIX, Linux and Windows platforms. Aldec is dedicated and responsive to serving its customers’ needs. It is recognized that to be productive in today’s market and to best serve customers in the future, new technologies and innovations that go beyond traditional methods of conducting business in the EDA industry must be pursued. Aldec is committed to customer service and is actively developing a company that will evolve along with its customers’ designs. Additional information about Aldec is available at http://www.aldec.com.



Active-HDL is a trademark of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners

Contact:        
Megan Moran        
Aldec, Inc.
(702) 990-4400 ext. 201        
Email Contact




Review Article Be the first to review this article

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Jobs
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Staff Software Engineer - (170059) for brocade at San Jose, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Technical Support Engineer for EDA Careers at Freemont, CA
Upcoming Events
EDI CON China 2017! at Shanghai Convention & Exhibition Center of International Sourcing (SHCEC) No.2739 West Guangfu Road Putuo District, Shanghai (200062) China - Apr 25 - 27, 2017
2017 SEMICON Southeast Asia at SPICE Arena Penang Malaysia - Apr 25 - 27, 2017
2017 IoT Developers Conference at Santa Clara Convention Center California - Apr 26 - 27, 2017
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy