Verisity and Cold Spring Engineering Announce eVC for SPI 4.2

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 9, 2002--Verisity, Ltd. (Nasdaq: VRST), the leading provider of functional verification automation tools, and Cold Spring Engineering, a member of Verisity's Verification Alliance(TM) program, today announced the availability of a new e Verification Component (eVC(TM)) from Cold Spring Engineering. The SPI 4.2 eVC is the newest addition to a growing list of configurable, reusable, plug-and-play verification components for standard interfaces based on Verisity's high-level verification language, e. This eVC, developed using Specman Elite(TM), significantly reduces the time necessary to create the verification infrastructure and automated testbench environment required for verifying today's designs and complex SoCs. Following Verisity's e Reuse Methodology (eRM(TM)), the SPI 4.2 eVC is on schedule to become eRM compliant by the end of this year (see related release, "Verisity Announces e Reuse Methodology," dated September 9, 2002).

"Having developed over twenty verification components, we obviously recognize the tremendous productivity enhancing capabilities of reusable components within a verification environment," remarked Cold Spring CTO Jim Kornell. "With the announcement of our new SPI 4.2 eVC, Cold Spring Engineering is providing verification teams yet another efficiency tool to expedite the verification process without sacrificing quality. Verification teams can now verify designs implementing this protocol faster than ever before."

"Without a doubt, Verification Alliance partners like Cold Spring Engineering are enabling our customers to get through verification bottleneck much quicker and easier," said Dave Tokic, director of strategic marketing for Verisity. "Together with Specman Elite(TM), eVCs deliver the most effective solution offered in the market today. Cold Spring Engineering has been consistently delivering the tools needed to not only keep up with increasing design complexity, but actually reduce verification cost and time-to-market, while improving quality."

About the SPI 4.2 eVC

The SPI 4.2 eVC is fully compliant with the Optical Internetworking Forum Serial Packet Interface Level 4, Phase 2 specification (January 2001). It includes a configurable pattern generator for injecting random, directed-random, as well erroneous test cases, and an example scoreboard implementation. Test cases include generation of Ethernet II or Ethernet 802.3, ATM UNI or ATM NNI, PPP, or random packets, with automatic or user-controlled content for all frame/packet fields. The number of ports, port arbitration, status generation and bandwidth, skew/deskew, and many other functional characteristics are user-configurable, so testing focus can be as tight or as broad as the verification need. With its well-documented and easy-to-use interface, it ensures thorough checking for SPI 4.2 designs.

For complete features of the SPI 4.2 eVC, please contact Email Contact or look on the Cold Spring Engineering web site

e Verification Components

Each eVC includes three integrated components: a stimuli generator for injecting and generating traffic, monitors and checkers for viewing outputs and checking protocol rules, and coverage reports showing the functional coverage of scenarios. They can be used in a variety of design applications and are available for a wide array of industry standards.

eVCs foster verification reuse because they can easily be moved from module-level verification to SoC-level verification, as well as from one chip design to another. Users can drop them into their designs and drastically cut the time it takes to create a verification environment.

For a complete listing of eVCs available, please visit and customers can log in to

e Reuse Methodology (eRM)

eRM provides dramatic functional verification productivity gains, most notably for advanced ASICs, SoCs and processors. eRM is a complete reuse methodology that codifies the best practices for eVC development. eRM delivers a common eVC usage model, and ensures that all eRM compliant eVCs will interoperate seamlessly regardless of origin. In addition, new eRM technology in Specman Elite, Verisity's flagship testbench automation tool, increases the power of eRM compliant eVCs to generate and synchronize complex multi-transaction scenarios.


The SPI 4.2 eVC works with Verilog and VHDL devices and simulators that are supported by Specman Elite and will be available starting August 2002. The eVC comes with complete documentation and example configurations for typical verification environments.

About Cold Spring Engineering

Cold Spring Engineering has developed and continues to develop a variety of reusable verification components. Cold Spring is experienced in a wide range of telecom and bus protocols at both the design and the verification levels, and has expertise in verifying complex ASICs, SoCs, and custom ICs.

Cold Spring views reusable verification components as the future of verification for most designs. Using effective verification methods and thoroughly tested components, verification engineers will be able to not only keep up with increasing design complexity, but actually reduce verification cost and time-to-market, while improving quality. Cold Spring's aggressive development of eVCs pushes a new trend to lower verification costs.

Cold Spring supports its reusable verification components with a full suite of verification services, from requirements analysis through test planning through complete verification and reporting.

Cold Spring Engineering is partnered with Verisity through the Verification Alliance program to make design verification faster, better, and cheaper. For more information on Cold Spring Engineering visit or write to us at Email Contact.

About Verisity

Verisity is the leading provider of proprietary technologies and software products used to efficiently verify designs of electronic systems and complex integrated circuits that are essential to high growth segments of the electronics industry. Verisity's products automate the process of detecting flaws in these designs, enabling customers to deliver higher quality products, accelerate time-to-market and reduce overall product development costs.

Verisity Design, Inc.'s principal executive offices are located in Mountain View, CA. The Company's principal research and development offices are located in Rosh Ha'ain, Israel. For more information, see Verisity's web site at

Verisity is a registered trademark of Verisity Design, Inc. eVCs, Specman Elite and Verification Alliance are trademarks of Verisity Design, Inc. All other trademarks are the property of the respected owners and should be treated as such.

     Verisity Design, Inc.
     Ric Chope, 650/934-6820
Email Contact

Source: Verisity Design, Inc. Today's News On The Net - Business Wire's full file on the Internet

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