Verisity Announces e Reuse Methodology (eRM) for Reusable, High-Quality, Verification Component Development
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Verisity Announces e Reuse Methodology (eRM) for Reusable, High-Quality, Verification Component Development

eRM Boosts Productivity and Ensures Interoperability for all eVCs


MOUNTAIN VIEW, CA -- September 9, 2002 -- Verisity Ltd. (Nasdaq:VRST), the leading provider of functional verification automation, today announced a new methodology for developing reusable verification components. Through the e Reuse Methodology (eRM�), the company is promoting best practices among e Verification Component (eVC™) developers by providing comprehensive guidelines and best-known methods for eVC development.

eRM provides dramatic functional verification productivity gains, most notably for advanced ASICs, SoCs and processors. eRM is a complete reuse methodology that codifies the best practices for eVC development. eRM delivers a common eVC usage model, and ensures that all eRM compliant eVCs will interoperate seamlessly regardless of origin. In addition, new eRM technology in Specman Elite™, Verisity’s flagship testbench automation tool, increases the power of eRM compliant eVCs to generate and synchronize complex multi-transaction scenarios.

“With verification consuming 60-80% of the manpower on complex chip projects, improving verification productivity is an economic necessity," said Moshe Gavrielov, Verisity CEO. “Verification reuse directly addresses higher productivity, increased chip quality and overall verification investment. The fact that over 70 eVCs have been created in just two years is a testament to the serious need for verification reuse. eRM is the breakthrough technology required to create reusable verification environments and to ensure that all verification components effectively interoperate.”

Verification Reuse Challenges
Today’s complex chips commonly incorporate many different protocols, interfaces and processors. Assembling appropriate verification environments requires efficient integration of reusable, plug-and-play verification components. Achieving reusability requires that all components be built and packaged uniformly. Reusability becomes even more challenging when design teams all over the world create verification components that need to fit together seamlessly. Every aspect of the component, including basic naming conventions and coding styles, debug message conventions, user interfaces, and interactions between components must be standardized in order to assure interoperability.

“As a world leader in the development and licensing of reusable Platform IP, ARM faces many complex verification challenges,” stated Ian Thornton, PrimeXsys product manager, ARM. “Verification reuse is essential for our own productivity and to reduce time-to-market for our PrimeXsys™ Platform licensees. The capabilities introduced in Verisity’s eRM make a significant contribution to meeting these requirements by enabling a framework for reuse. For this reason we developed our PrimeXsys verification methodology to be eRM-compatible.”

Complete Verification Reuse Methodology
eRM delivers the best known methods for developing eVCs through a common user model and enhanced Specman Elite functionality. eRM includes three major elements:

Customers and Verification Alliance Partners Embrace eRM
Verisity’s customers and partners are now proliferating eRM within their organizations. Ten eRM compliant eVCs have already been developed and many more are in development by customers, Verisity, and Verification Alliance ™ partners throughout the world.

“Agere frequently verifies multi-million gate devices,” said Don Friedberg, director of design methodologies at Agere Systems. “Agere has invested in creating reusable verification components (eVCs) to optimize our efficiency. This is proving to be a winning strategy among our design teams. We are extremely pleased that Verisity is delivering eRM to ensure that all eVCs will seamlessly plug-and-play. We believe this is important not only for the eVCs developed within Agere Systems, but for eVCs developed by members of Verisity's Verification Alliance."

Verisity’s Verification Alliance partners are also rapidly adopting eRM practices. eInfochips, a leading commercial eVC provider based in Milpitas, California, immediately saw the benefits of eRM.

eRM breaks through the barriers that have traditionally stalled reuse initiatives and simplifies our job as eVC developers,” stated Nilesh Ranpura, project manager at eInfochips. “eRM’s cookbook approach to writing and packaging e code enables all our developers to create consistent, high-quality eVCs. This is a big win for eVC users.”

Pricing and Availability
eRM is provided at no charge to Specman Elite customers. Currently in use by qualified customers and partners, eRM will be available to all Verisity customers in November 2002. The eRM Advanced Training course is available immediately. Through the end of 2002, eRM Advanced Training will be provided at no charge to qualified eVC developers.

About Verisity
Verisity is the leading provider of proprietary technologies and software products used to efficiently verify designs of electronic systems and complex integrated circuits that are essential to high growth segments of the electronics industry. Verisity's products simplify the process of detecting flaws in these designs, enabling customers to deliver higher quality products, accelerate time-to-market and reduce overall product development costs.

Verisity Design, Inc.'s principal executive offices are located in Mountain View, CA. The Company's principal research and development offices are located in Rosh Ha'ain, Israel. For more information, see Verisity's web site at www.verisity.com.

For more information contact:
Ric Chope
Verisity Design, Inc.
(650) 934-6820
Email Contact


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Verisity is a registered trademark of Verisity Design, Inc. eVCs, Specman Elite and Verification Alliance are trademarks of Verisity Design, Inc. All other trademarks are the property of the respected owners and should be treated as such.