Learn About Assertion-Based Verification in the Intelligent Testbench for SoC Design as Verify 2002 Gets Underway October 3

Sponsors Include Axis, CoWare, Denali, Forte, Novas, Sun Microsystems, Verplex


AUSTIN, TEXAS, September 9, 2002 - Verify 2002, a series of eight educational seminars on Assertion-Based Verification in the Intelligent Testbench for SOC Design, kicks off Wednesday, October 3, here at the Renaissance Austin Hotel. The series continues through November 5 at select cities throughout the United States and Canada, and travels to Munich, Germany, Thursday, October 10.

Each seminar includes two featured speakers. Harry Foster, chairman of Accellera's Formal Language Committee and author of "Principles of Verifiable RTL" and the soon-to-be-released "Assertion-based Design," will present a tutorial on why, where and how to use assertions in integrated circuit (IC) designs. Anders Nordstrom, director of engineering at PacketDNA and a member of the IEEE 1364 Verilog Standards Committee and the Accellera SystemVerilog Committee, will take participants through the evolution of verification methodologies, and provide a real-world example of verification methodologies associated with advanced telecom designs.

This year's dates and locations are:

  • Thursday, October 3 -- Austin, Texas
  • Thursday, October 10 -- Munich, Germany
  • Tuesday, October 15 -- San Jose, California
  • Thursday, October 17 -- San Diego, California
  • Tuesday, October 22 -- Westford, Massachusetts
  • Thursday, October 24 -- Ottawa, Canada
  • Tuesday, October 29 -- Denver, Colorado
  • Tuesday, November 5 -- Santa Clara, California
Sponsor companies and presenters include Axis Systems, CoWare, Denali Software, Forte Design Systems, Novas Software, Sun Microsystems, and Verplex Systems.

These educational seminars have been designed to help electronic engineers learn how to incorporate and use assertion-based languages and tools in their design flows and advance towards an intelligent testbench solution.

Agenda sessions include:

  • "An Assertion Methodology for Emulation" by Axis Systems
  • "Transaction Level Hardware and Software Verification for SoCs" by CoWare
  • "Using Memory-Based Assertions for System Verification" by Denali Software
  • "Functional Coverage and High-Level SystemC Modeling for RTL Verification" by Forte Design Systems
  • "Debugging for the Intelligent Testbench" by Novas Software
  • "Intelligent Resource Management with SunGrid Engine" by Sun Microsystems
  • "An Assertion-Based Formal Methodology for Functional Closure" by Verplex Systems
The Verify Seminars, which began in 1997, are free of charge to any design engineer, verification engineer or engineering manager who registers at http://www.verifyseminars.com.

For more information, contact:
Scott Sandler
Novas Software
Tel: 1-888-NOVAS-38
Fax: (408) 467-7889
Email Contact

All trademarks mentioned herein are the property of their respective owners.



Review Article Be the first to review this article
CST: Webinar October 19, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
DVCon Europe 2017: Munich and So much more
More Editorial  
Jobs
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
Upcoming Events
Preparing for the Cognitive Era: Education, Occupation and You at SJSU Student Union Theater 211 South 9th Street San Jose CA - Oct 18, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
15th IEEE/ACM ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
ESTIMedia 2017 at Seoul Korea (South) - Oct 19 - 20, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise