MediaPhy Licenses Tensilica's Diamond Standard 108Mini Processor Core

SANTA CLARA, Calif.—(BUSINESS WIRE)—October 15, 2007— Tensilica(R), Inc. today announced that MediaPhy Corporation, of San Jose, Calif., has licensed the Diamond Standard 108Mini, the industry's lowest power 32-bit processor core for SOC (system-on-chip) design. MediaPhy will use the Diamond Standard 108Mini in its next generation mobile audio and video entertainment designs.

"One of our main target application areas is battery operated mobile/portable devices where power consumption is a very critical factor," stated Mohammad Moradi, co-founder and executive vice presdient of Engineering at MediaPhy. "As such, we have chosen the Tensilica Diamond Standard 108Mini processor core to benefit from its low power consumption and small area at the same time."

"Companies like MediaPhy, who are designing innovative new chip designs for portable devices, inspire us to keep pushing the envelope for more performance at lower power," stated Antonio J. Viana, Tensilica's senior vice president of worldwide sales. "We are happy to make a strong contribution to their first products."

About MediaPhy Corporation

Based in Silicon Valley, California, MediaPhy Corporation is a fabless semiconductor company developing solutions for next generation mobile audio and video entertainment applications. Targeting cell phones, portable media players (PMP), laptops, PCs, PDAs and automotive entertainment applications, MediaPhy's technology is designed to enable mobile television on a worldwide basis. For more information on the company and its technology please visit www.mediaphy.com.

About Tensilica

Tensilica offers the broadest line of controller, CPU and specialty DSP processors on the market today, in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. Tensilica's low-power, benchmark proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. All Tensilica processor cores are complete with a matching software development tool environment, portfolio of system simulation models, and hardware implementation tool support. For more information on Tensilica's patented approach to the creation of application-specific building blocks for SOC design, visit www.tensilica.com.

Editors' Notes:

-- Tensilica and Xtensa are registered trademarks belonging to Tensilica Inc. All other company and product names are trademarks and/or registered trademarks of their respective owners.

-- Tensilica's announced licensees include ALPS, AMCC (JNI Corporation), Aquantia, Astute Networks, Atheros, ATI, Avago Technologies, Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, Cypress, Crimson Microsystems, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes Network Systems, Ikanos Communications, LG Electronics, Lucid Information Technology, Marvell, MediaPhy, MediaWorks, NEC Laboratories America, NEC Corporation, NetEffect, Neterion, Nippon Telephone and Telegraph (NTT), NVIDIA, Olympus Optical Co. Ltd., sci-worx, Seiko Epson, Solid State Systems, Sony, STMicroelectronics, Stretch, TranSwitch Corporation, u-Nav Microelectronics and Victor Company of Japan (JVC).

Contact:

Tensilica, Inc.
Paula Jones, 408-327-7343
Email Contact
or
Powelson Communications
Erika Powelson, 831-424-1811
Email Contact




Review Article Be the first to review this article
CST: Webinar September 14, 2017

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Real Intent: Leveraging on Investments
More Editorial  
Jobs
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
FPGA Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Upcoming Events
IEEE Electronic Design Processing Symposium 2017 at 673 S. Milpita Blvd Milpitas CA - Sep 21 - 22, 2017
CODES+ISSS 2017, Oct 15-20, 2017, Lotte Hotel, Seoul, South Korea at Lotte Hotel Seoul Korea (North) - Oct 15 - 20, 2017
DVCon 2017 Europe, Oct 16 - 17, 2017, Munich, Germany at Holiday Inn Munich City Centre Munich Germany - Oct 16 - 17, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise