SAN JOSE, Calif. & ST. ALBANS, England—(BUSINESS WIRE)—September 9, 2007— ARC International (LSE: ARK) and Cadence Design Systems, Inc. (NASDAQ:CDNS), today announced a new automated Common Power Format (CPF)-enabled low-power reference design methodology (LP-RDM) has been implemented in ARChitect, ARC's patented processor configuration tool. This LP-RDM together with the Cadence(R) Low Power Solution ensures that ARC's new Energy PRO technology is captured in RTL and implemented consistently throughout the design flow to GDSII. Users of the reference design flow may achieve up to a four-fold reduction of IP core power. See companion ARC press release dated September 10, 2007 for more details on Energy PRO.
"ARC and Cadence have been jointly developing a reference design
flow based on the SI2 industry standard Common Power Format," said
Michael Horne, group director, Industry Alliances at Cadence. "The new
design flow represents the culmination of this effort. Using the
Cadence Low Power Solution enabled by CPF, ARC has successfully
employed a standard 90nm low-power standard cell library to perform
netlist synthesis, verification, floorplanning, and routing of an ARC
core to a TSMC 90nm target process. The result was a right-first-time
test design that achieved its target power specifications."
"ARC and Cadence have worked together to make great strides in
achieving the lowest power in SoC designs using ARC's configurable
cores and subsystems at joint customers," said Paul Holt, vice
president, product development and services at ARC International. "The
result of our experiments with the new flow shows that customers using
ARC's Energy PRO technology and employing the new LP-RDM based on
Cadence technology will achieve power savings of up to four fold over
conventional low-power flows of the past."
Energy PRO in the Encounter Low-Power Flow
The ability to custom configure a processor core or subsystem
using ARChitect is a fundamental advantage provided to SoC designers
of ARC-based(TM) chips. ARC's future products based on Energy PRO
technology will extend this advantage by incorporating specific
power-management features in the product. ARC will provide development
tools which will recognize the power intent of the product and ensure
that the hardware design achieves its optimal energy efficiency.
Cadence Low-Power Solution scripts are integrated into ARC's
configuration tool in a Reference Design Flow (RDF) library. ARChitect
allows the designer to implement various Energy PRO features while
taking advantage of Virage Logic's Area, Speed and Power (ASAP)
Logic(TM) standard cell libraries and Ultra-Low-Power standard cell
architecture. ARChitect then produces RTL containing the Energy PRO
design intent for input to the Cadence Encounter(R) digital IC design
platform - a key component of the Cadence Low-Power Solution. Using
the industry standard SI2 Common Power Format, the Encounter platform
provides RTL to netlist synthesis, verification, floor planning and
routing for a TSMC 90nm process technology. Thus SoC designers can
easily configure an Energy PRO processor and be assured that all its
low-power capability automatically propagates through the entire
Encounter flow to final layout.
The new low-power reference design methodology (LP-RDM)
implemented in ARChitect is available now. For more information,
contact ARC sales representatives or e-mail email@example.com.
About Cadence Design Systems, Inc.
Cadence enables global electronic-design innovation and plays an
essential role in the creation of today's integrated circuits and
electronics. Customers use Cadence(R) software and hardware,
methodologies, and services to design and verify advanced
semiconductors, consumer electronics, networking and
telecommunications equipment, and computer systems. Cadence reported
2006 revenues of approximately $1.5 billion, and has approximately
5,200 employees. The company is headquartered in San Jose, Calif.,
with sales offices, design centers, and research facilities around the
world to serve the global electronics industry. More information about
the company, its products, and services is available at
About ARC International plc
ARC International is the world leader in configurable media
subsystems and CPU/DSP processors. Used by over 140 companies
worldwide, ARC's configurable solutions enable the creation of highly
differentiated system-on-chips (SoCs) that ship in hundreds of
millions of devices annually. ARC's patented subsystems and cores are
smaller, consume less power, and are less expensive to manufacture
than competing products.
ARC International maintains a worldwide presence with corporate
and research and development offices in Silicon Valley and St. Albans,
UK. For more information visit www.ARC.com. ARC International is
listed on the London Stock Exchange as ARC International plc
Cadence and Encounter are registered trademarks, and, the Cadence
logo is a trademark of Cadence Design Systems, Inc. All other
trademarks are the property of their respective owners.
ARC and the ARC logo are trademarks or registered trademarks of
ARC International. All other brands or product names contained herein
are the property of their respective owners. This press release may
contain certain "forward-looking statements" that involve risks and
uncertainties, including the development, implementation, and release
of features described herein. These are at the sole discretion of ARC
International. Licenses from 3rd parties for certain software and
essential patents may be required depending on licensee's
use/implementation. For other factors that could cause actual results
to differ, visit the company's Website as well as the listing
particulars filed with the United Kingdom Listing Authority and the
Registrar of Companies in England and Wales.