Averant Announces Release of SolidPC 2.0, ARM AMBA 3 Assured Status

HAYWARD, Calif.—(BUSINESS WIRE)—August 28, 2007— Averant Inc., a leading provider of advanced verification technology for RTL designs, today announced the achievement of AMBA(R) 3 Assured status for SolidPC(TM) 2.0, Averant's property checking product for AMBA interconnect protocol compliance.

SolidPC's combination of ARM(R) technology-developed and endorsed AMBA rule sets, the Solidify First in Formal(TM) property checking engine, and a purpose built, easy to use, graphical user interface makes SolidPC the tool of choice for AMBA protocol verification. As users most often use only a subset of the AMBA protocol, SolidPC allows selection of the AMBA rule set being verified at the click of a menu button. SolidPC 2.0 adds a number of important features, but most importantly adds support for the AMBA 3 AXI(TM) protocol and a multicore processing environment. The multicore processing environment enables a nearly linear speedup in run time, with tests showing a 3.96 increase in performance for SolidPC on a 4-processor machine.

Other key features in SolidPC 2.0 include pushbutton integration to simulators for debug, and the addition of converse protocol rules. When SolidPC determines that there is an issue with a protocol rule, it produces a testbench and waveform trace to allow the user to analyze the rule failure within a traditional simulation environment. This testbench, in the RTL language, can be run at the push of a button on any of the most popular simulators to allow the user to debug in their familiar environment. The converse rules have been developed and implemented where appropriate, to prove that unintended behavior cannot happen. For example, if the user's design is not intended to support burst transfers, and this rule is de-selected in the SolidPC GUI, it enables a converse rule to be checked, verifying that burst transfers can never happen.

"As a developer of leading edge IP products, verification is critical to our success and the success of our customers," said Purna Mohanty, vice president of engineering for ASIC Architects. "SolidPC is helping us to get out higher quality products in a shorter amount of time."

SolidPC was the first formal verification product for AMBA interconnect compliance to be endorsed by ARM, in 2003, and remains as the only formal verification product to have achieved AMBA 3 Assured status. The ARM AMBA Assured program is meant to provide AMBA users easy access to tools that have gone through the rigorous certification process by ARM.

"We have worked closely with Averant engineers to ensure tight compliance of the SolidPC 2.0 tool with the AMBA 3 AXI specification," said Rob Kaye, AMBA Portfolio Manager at ARM. "The use of such formal methods will enable our mutual customers to efficiently and thoroughly validate their AMBA 3 AXI technology-based SoCs and in so doing, reduce overall chip verification time."

"Static functional verification is a natural fit for protocol verification," said Ramin Hojati, CEO of Averant. "Enabling designers to find the bugs in their bus interface earlier in the design cycle saves valuable man-hours later in the project and accelerates verification closure."

Averant is a member of the ARM Connected Community.

Availability

SolidPC 2.0 is available now on Linux, Windows and Solaris platforms.

About Averant

Averant Inc., founded in 1997, is a privately held EDA firm pioneering new methodology and technologies for static formal verification. Averant's flagship product is Solidify, a robust formal verification engine that provides the basis for property-based design verification, protocol verification, timing constraint verification, and automatic design checks -- all without the need for simulators or test vectors. These tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, see our web site at www.averant.com

Contact:

Averant, Inc.
Larry Lapides, +1-925-519-1234
Email Contact




Review Article Be the first to review this article
SI2

AMIQ: dvteclipse

Featured Video
Editorial
Peggy AycinenaIP Showcase
by Peggy Aycinena
Hal Barbour: 8 Grand Challenges in IP
More Editorial  
Jobs
LVS for PDK Design Engineer SILICON VALLEY for EDA Careers at San Jose, CA
LVS PEX DESIGN ENGINEERS SILICON VALLEY for EDA Careers at San Jose, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Upcoming Events
EMC PCB Design Integration at 13727 460 Ct SE North Bend WA - Jun 6 - 9, 2017
DAC 2017 Conference at Austin TX - Jun 18 - 22, 2017
2017 FLEX Conference at Monterey Conference Center 1 Portola Plaza, Monterey CA - Jun 19 - 22, 2017
MPSoc Forum 2017 - July 2 - 7, 2017, Les Tresoms Hotel, Annecy, France at Les Tresoms Hotel Annecy France - Jul 2 - 7, 2017
NEC: CyberWorkbench
Verific: SystemVerilog & VHDL Parsers
DownStream: Solutions for Post Processing PCB Designs
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy