"We are pleased to welcome Patrizia to our executive team as we continue to expand our operations," said Dr. Ajoy Bose. "Patrizia is a strong addition to our seasoned management team, joining the company at an important time in the company's evolution. She gives us a diverse and deep skill set which we believe will help take the organization to the next level. Patrizia is a financial leader with an established track record in building the financial infrastructure necessary to support growth. I am confident in her ability to significantly enhance Atrenta's financial and operational excellence."
Patrizia Owen has spent the past 15 years focusing on financial management for pre-IPO and early-stage companies, most recently serving as CFO of DigitalPersona. Before joining DigitalPersona, Ms. Owen was the CFO of inOvate Communications Group, funding early-stage investments in a wireless infrastructure. Prior to inOvate, she served as CFO for Beatnik, Inc. and represented the company to the banking and legal community during its IPO preparations. Earlier, she played an integral role in the merger, and subsequent public offering of I/Pro with Engage, Inc., a majority-owned operating company of CMGI, Inc. As VP of Corporate Development at Compression Labs, Ms. Owen was actively involved in the merger of that company with VTel. Previously, Ms. Owen held financial operations positions with Amgen and Hewlett-Packard. She holds an MBA from the University of British Columbia, Vancouver, Canada and a BA in Economics from the University of Western Ontario in London, Canada.
"I am delighted to join Atrenta and work with such a talented and focused management team," said Ms. Owen. "Atrenta represents a significant opportunity given the compelling market need for a comprehensive tool-suite to improve RTL design. I am confident that Atrenta's position as the definitive leader in its space will be solidified as the company continues its rapid growth."
Atrenta is the leading provider of early design closure solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to optimize their designs early in RTL phase for linting, clock domain crossings (CDC), power estimation and reduction, design for test (DFT), constraints generation and validation including timing exceptions, and RTL prototyping. Atrenta optimized RTL delivers up to 30% efficiency gains in chip integration, implementation and verification phases. Atrenta has over 120 customers, including the world's top 10 semiconductor companies. For more information, visit www.atrenta.com. Think Early Design Closure! Think Atrenta!
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.
Krishna Uppuluri, +1-408-453-3333