Design Automation Conference Booth 5260
"Many designs have been released using combinations of Functional Verification, Static Timing Analysis, and Equivalency Checking, which allow design teams to achieve confidence in function and timing," said Prakash Narain, CEO and President of Real Intent, Inc. "However there are two classes of paths which are left untimed or improperly verified using these flows. With our EnVision TCV design teams can achieve Proven Timing Closure and plug these holes in their verification flows."
Closing Timing Verification Holes with Proven Timing Closure Two sources of errors are not covered by typical functional verification, static timing, and equivalence checking flows: clock domain crossing signals and exceptions to default timing.
Clock domain crossing signals are not verified by simulation, emulation, prototyping or equivalency checking, nor are they checked by static timing, where in fact they are typically marked as false paths. Meridian (announced in April this year), part of EnVision TCV, is a new approach to CDC verification, and is engineered to verify that data traversing asynchronous clock domains on ASIC, SOC or FPGA devices is received reliably. After quick automatic setup, Meridian formally verifies both the structure and the protocols required for CDC safe design, then pinpoints design problems with an absolute minimum amount of manual sign-off.
PureTime, also part of EnVision TCV, removes the risk of errors in Synopsys Design Constraint (SDC) timing exceptions. Neither functional simulation, emulation, prototyping, nor static timing verifies the correctness of exceptions. PureTime's automatic processing dramatically improves project schedules when compared to manual review of exceptions. PureTime provides the accuracy of full sequential analysis. Combinatorial only solutions can not analyze multi cycle paths, and will erroneously invalidate false paths that full sequential analysis correctly verifies.
Price and Availability
EnVision TCV is available now for $97k.
About Real Intent
Real Intent is extending breakthrough formal technology to critical problems encountered by design and verification teams worldwide. Real Intent's products dramatically improve the functional verification efficiency of leading edge application specific integrated circuit (ASIC), system-on-chip (SOC), and Field Programmable Gate Array (FPGA) devices. Over 40 major electronics design houses, including Sun Microsystems, AMD, nVidia, and NEC Electronics use Real Intent software.
Real Intent is headquartered at 505 North Mathilda Avenue, Suite 210, Sunnyvale, CA 94085, phone: (408) 830-0700 fax: (408) 737-1962, web: www.realintent.com, e-mail: Email Contact.
For more information contact:
(408) 830-0700 x212
Valley PR for Real Intent
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