Certess to Present Embedded Tutorial Panel at the 2007 Design Automation and Test Conference

CAMPBELL, Calif.—(BUSINESS WIRE)—April 16, 2007— Certess, Inc., an electronic design automation (EDA) company focusing on functional qualification for companies that create and integrate complex design blocks or intellectual property (IP), today announced that the company will present a tutorial on "Heterogeneous Systems on Chip and Systems in Package" at the DATE (Design Automation and Test Europe) Conference held on April 17-19, 2007 in Nice, France.
WHO:    Certess, Inc.

WHAT:   Embedded Tutorial Panel: "Heterogeneous Systems on Chip and
        Systems in Package." Mark Hampton, Certess' chief technology
        officer and co-founder, will present.  This embedded tutorial
        and panel aims to confront several points of view on the
        miniaturization of existing systems to the creation of
        specific integrated functions, MEMS and non-electronic devices
        that are being integrated to create heterogeneous systems in
        package and systems on chip. This tutorial session will be
        moderated by Ian O'Connor, Ecole Centrale de Lyon, FR and
        additional speakers are Krish Chakrabarty, Duke University,
        Nicolas Delorme, CEA-LETI and Juergen Hartung, Cadence,
        Europe.

WHERE:  2007 DATE Conference, Acropolis, Nice, France. For more
        information please visit www.date-conference.com.

WHEN:   Wednesday, April 18, 2007 at 11:00 AM.


About Certess

Certess, Inc is an electronic design automation (EDA) company focusing on functional qualification for companies that create and integrate complex design blocks or intellectual property (IP). The company's technology will provide verification engineers with an objective way to evaluate and improve the completeness of the verification environment, resulting in a shorter and more predictable process to integrate SoC designs. The company is headquartered in Silicon Valley. For additional information, see www.certess.com.

Contact:

Cayenne Communication
Michelle Clancy, 252-940-0981
Email Contact




Review Article Be the first to review this article
SI2

AMIQ: dvteclipse

Featured Video
Editorial
Peggy AycinenaIP Showcase
by Peggy Aycinena
Grant Pierce: Grand Challenges in IP
More Editorial  
Jobs
LVS PEX DESIGN ENGINEERS SILICON VALLEY for EDA Careers at San Jose, CA
LVS for PDK Design Engineer SILICON VALLEY for EDA Careers at San Jose, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Upcoming Events
EMC PCB Design Integration at 13727 460 Ct SE North Bend WA - Jun 6 - 9, 2017
DAC 2017 Conference at Austin TX - Jun 18 - 22, 2017
2017 FLEX Conference at Monterey Conference Center 1 Portola Plaza, Monterey CA - Jun 19 - 22, 2017
MPSoc Forum 2017 - July 2 - 7, 2017, Les Tresoms Hotel, Annecy, France at Les Tresoms Hotel Annecy France - Jul 2 - 7, 2017
NEC: CyberWorkbench
ClioSoft
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy