Renesas Technology Chooses Synopsys IC Compiler Solution for SOC Design Flow

Higher Performance for Multi-Mode Designs Drives Selection

MOUNTAIN VIEW, Calif., March 27 /PRNewswire-FirstCall/ -- Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Renesas Technology Corp. has adopted Synopsys' IC Compiler next-generation place-and-route solution for its production IC design flow. The growing complexity of Renesas' designs required them to meet timing in several different functional modes. After thoroughly evaluating all available options, Renesas selected Synopsys' IC Compiler solution for its ability to achieve desired chip performance by concurrently optimizing all timing modes through its true multi-mode capability. Renesas also reaped the benefits of significantly faster turnaround time and enhanced ease-of-use.

"Having our chips work at high speed across many different functional modes has been a growing challenge for us, even with mainstream consumer designs," said Teruaki Harada, department manager, DFM & EDA Technology Development Dept. at Design Technology Div. at Renesas Technology Corp. "We have relied on Synopsys tools to help us with our many challenging designs and now, with the IC Compiler solution, we have addressed the very pressing issue of multi-mode timing."

Renesas evaluated all available multi-mode approaches, including sequential and merging techniques, using a demanding set of 15 test cases which included a large 0.13-micron consumer design with more than 3.5-million gates and 5 operating modes. Renesas found that the IC Compiler solution satisfied all requirements and delivered desired performance for multi-mode optimization. The IC Compiler physical implementation solution relies on Extended Physical Synthesis (XPS) technology to increase optimization efficiency, which not only offered Renesas improved clock speed results, but also enabled the designers to reduce the total cell area of the design. XPS is a new architecture that combines synthesis, placement, clock and routing into a unified optimization environment. As a result, Renesas found the IC Compiler solution to be faster and significantly easier to use than alternate solutions, even for single-mode designs.

"Renesas has a long history of working closely with Synopsys on their most challenging designs," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "By selecting our IC Compiler solution for its true concurrent multi-mode optimization capability, Renesas can now reduce design time while increasing performance."

About IC Compiler

The IC Compiler tool is Synopsys' next-generation place-and-route solution. It provides superior results and faster time-to-results by extending physical synthesis to full place-and-route, and by enabling signoff-driven design closure. Current-generation solutions have a limited horizon because placement, clock tree, and routing are separate, disjointed operations. IC Compiler's Extended Physical Synthesis (XPS) technology breaks down the walls between these steps by extending physical synthesis to full place-and-route. IC Compiler has a unified, TCL-based architecture that implements innovations and harnesses some of the best Synopsys core technologies. It is a complete place-and-route system with everything necessary to do next-generation designs, including physical synthesis, placement, routing, timing, signal integrity (SI) optimization, power reduction, design-for-test (DFT), and yield optimization.

About Synopsys

Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at www.synopsys.com.

NOTE: Synopsys is a registered trademark of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

    NEWS RELEASE
    Editorial Contact:
    Sheryl Gulizia
    Synopsys, Inc.
    650-584-8635
    
Email Contact

    Rachel Modena Barasch
    MCA, Inc.
    650-325-7547
    
Email Contact

Web site: http://www.synopsys.com//


Rating:


Review Article Be the first to review this article
Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Computer History Museum: the Future of War is Here
More Editorial  
Jobs
Senior SW Developer for EDA Careers at San Jose, CA
REVISED***Director Product Line RF/IC for EDA Careers at San Jose, CA
Upcoming Events
“Empowering Leadership with WIT and WISDOM” at SEMI 673 South Milpitas Blvd. Milpitas CA - Nov 28, 2017
Artificial Intelligence and Convolution Neural Networks Discussion at San Jose State University Student Union Theater San Jose CA - Dec 4, 2017
Silicon Valley's Only Comprehensive Embedded Systems Conference at San Jose Convention Center 150 W. San Carlos St. San Jose CA - Dec 5 - 7, 2017
Oski Technology’s Decoding Formal Club Meeting at The Conference Center San Jose CA - Dec 7, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise