Timing simulation of gate-level designs is still a common practice in IC verification - to augment static timing analysis, confirm gate-level engineering change orders (ECOs), and verify functional and structural tests that will be used to validate the actual silicon. The Siloti Replay module significantly reduces the signal data recording requirements that can slow gate-level simulation to a crawl and eliminates the need to re-run long, costly simulations when errors are detected.
"Timing closure is the number one issue facing many design teams today," said George Bakewell, director of product and technical marketing for Novas. "Our new Siloti Replay module accelerates the simulation-based process commonly used to detect and isolate timing problems. When timing errors are observed during simulation, engineers can use Replay to run short, quick simulations focused on the problematic time windows. The result is remarkably improved turnaround time."
Timing-Accurate Debug Flow
Gate-level timing simulation is notoriously slow and capturing enough data for effective debug only exacerbates the problem. Many design teams have adopted painful but necessary approaches to work around these issues - limiting timing simulations to only the most critical tests and paying the price of long, slow re-simulations to capture data when problems are detected. The Siloti Replay module addresses these issues by limiting the initial data dump to a relatively small set of essential signals and enabling fast, focused simulations to capture full signal data with timing for the time windows in which problems originate.
The Siloti SimVE(TM) visibility analysis engine is used to automatically derive the minimal set of "essential signals" required to drive the replay process. This serves to both accelerate the initial simulation and reduce the output dump file size. Users then perform an initial debug step to narrow the source of the problem in space (logic) and time, using the automated tracing capabilities available in the Novas Verdi(TM) Automated Debug System and applying the cycle-accurate SimVE data expansion capabilities to gain full visibility into the design.
The Siloti Replay module is then activated to run short, targeted simulations and capture timing-accurate signal data for the time windows of interest. These simulations can be run using any of today's popular simulators and are controlled through open application programming interfaces. Siloti Replay users realize significant efficiency gains because the follow-up simulation immediately jumps to the user-specified time window, eliminating the run-time usually spent getting to that point. These timing-accurate simulations can be performed multiple times for different time windows using the same baseline essential signal dump, and the results further analyzed and debugged with the Verdi system to better understand the cause-and-effect relationships and diagnose the root cause of timing problems.
Pricing & Availability
The Siloti Replay module is immediately available as an add-on option to the Siloti SimVE product at the U.S. list price of $15,000 for an annual subscription license. The Siloti SimVE product starts at $25,000 U.S. More information on Novas' Siloti products and recent awards for innovation in chip verification is available online at: www.novas.com/Solutions/Siloti/.
About Siloti Visibility Enhancement
The Novas Siloti visibility enhancement products transform verification methodologies by eliminating the overhead associated with dumping data for all the signals in a design. They provide full visibility of internal signals by identifying the minimal set of signals for dumping, generating "on-demand" data for the remaining signals, and correlating gate-level results to the register transfer level (RTL) source code. Used during full-chip simulation, emulation and first-silicon prototyping, Siloti products can dramatically improve the observability of internal signal behavior with minimal impact on verification performance.
Novas Software, Inc. is the leading provider of design comprehension solutions for engineers designing complex ICs, embedded systems and SoCs. The Novas Verdi(TM) Automated Debug and Siloti(TM) Visibility Enhancement products dramatically accelerate the process for understanding and correcting design problems starting from system-level specification through silicon implementation. Novas is headquartered in San Jose, Calif. with offices in Europe, Japan and Asia-Pacific. For more information, visit www.novas.com or email firstname.lastname@example.org.
Siloti, SimVE, and Verdi are trademarks of Novas Software, Inc. All other trademarks or registered trademarks are property of their respective owners.
For Novas Software, Inc., San Jose
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Laurie Stanley, 925-224-8762
Novas Software, Inc.
Rob van Blommestein, 408-467-7872