Cadence Digital IC Design Platform Enables Global Unichip to Complete Taiwan's First 65-NM Chip Design

SAN JOSE, CA -- (MARKET WIRE) -- Mar 11, 2007 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today said Global Unichip Corporation (GUC; TW:3443), a leading system-on-chip (SoC) design foundry, is the first Taiwan-based design company to complete a successful tapeout of a 65-nanometer device. The success of this 65-nanometer tapeout further strengthened GUC's advanced technology capabilities to serve the top tier customers worldwide. GUC used the Cadence® Low-Power Solution and SoC Encounter™ GXL RTL-to-GDSII system to achieve the tapeout.

"Targeting a 65-nanometer process technology is the state-of-the-art in semiconductor design," said Jim Lai, president and COO of GUC. "Success requires a tightly integrated design environment and an automated low-power design methodology. With comprehensive know-how of advanced technology designs, GUC used the combination of the Cadence Low-Power Solution and Encounter platform to build this low power design with over ten-million gates and implement it within seven weeks, which in turn helps GUC's customer to achieve a significant time-to-market advantage."

The GUC tapeout involved a customer design that is slated to move into production. GUC designed the chip using the Cadence SoC Encounter system, Encounter® Conformal® technology, and CeltIC® SI-aware nanometer delay calculator. GUC achieved higher quality of results using the design-for-yield features and design-for-manufacturing capabilities of SoC Encounter GXL, including virtual CMP and critical area analysis tools.

"We congratulate GUC on this achievement," said Chi-Ping Hsu, corporate vice president, IC Digital and Power Forward at Cadence. "GUC has clearly demonstrated a leading-edge design and implementation capability that targets advanced processes with state-of-the-art, low-power design techniques, and we are honored to have been part of it."

Many of the tools used by GUC in this design are also part of the Cadence Logic Design Team Solution, which helps logic design teams improve schedule predictability through plan-to-closure management and logical signoff -- in an integrated and holistic approach covering both design and verification. It represents another deliverable in Cadence's overall segmentation strategy, offering tailored solutions for specific types of engineering teams.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2006 revenues of approximately $1.5 billion, and has approximately 5,200 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

About Global Unichip Corp.

Global Unichip Corp. (GUC), a dedicated full service SoC (System On Chip) Design Foundry based in Taiwan, was founded in 1998. GUC provides total solutions from silicon-proven IPs to complex time-to-market SoC turnkey services. GUC is committed to providing the most advanced and the best price-performance silicon solutions through close partnership with TSMC, GUC major shareholder, and other key packaging and testing power houses. With state-of-the-art EDA tools, advanced methodologies, and experienced technical team, GUC ensures the highest quality and lowest risks to achieve first silicon success. GUC has established a global customer base throughout Greater China, Japan, Korea, North America, and Europe. Its track-record in complex SoC designs has brought benefits to customers in time to revenue at the lowest risk. For more information, please visit

Cadence, Encounter, Conformal, and CeltIC are registered trademarks and the Cadence logo and SoC Encounter are trademarks of Cadence Design Systems in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:
Dan Holden
Cadence Design Systems, Inc.

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Florence Chi
Global Unichip Corporation

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