"GamePlan has been embraced enthusiastically by verification teams around the world because of its ability to integrate formal verification easily into the overall verification plan," stated Jay Littlefield, director of technical marketing at Jasper Design Automation. "GamePlan is also highly valued by engineering management since it makes communication of verification status as simple as the push of a button. And, release 1.1 makes it even easier to track a changing verification plan and to readily share current status among design and verification teams."
GamePlan Verification Planner 1.1 is free, and currently available for download from the Jasper Design Automation corporate website. Check www.jasper-da.com/gameplan for details.
About GamePlan(TM) Verification Planner
GamePlan Verification Planner promotes collaboration within multiple verification teams by providing a single, comprehensive structured framework for identifying what design features need to be tested, what verification technologies are required for testing, and for prioritizing and tracking the progress of each feature tested. GamePlan Verification Planner fills the gaps in today's verification flow by adding a process for systematic verification that can fit into any environment, and that respects all verification methods, including formal verification, simulation and others. By providing GamePlan as a free tool, Jasper Design Automation is enabling systematic usage of formal verification alongside other technologies, and is taking a leading industry role in promoting a structured approach to verification.
About Jasper Design Automation
Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company with a mission of making full formal IC verification a competitive advantage for its customers. The company's flagship product, JasperGold Verification System, is the first verification product to deliver complete "deep formal" systematic verification, ensuring correctness where it matters most. JasperGold formally verifies that complex IC design blocks meet high-level requirements defined in their specifications, and also pre-verifies IP blocks for use under all usage modes, without any testbench development. JasperGold Express, Jasper's formal ABV solution, provides the industry's leading "light formal" solution, complementing simulation-based approaches by accelerating bug hunting as well as coverage attainment. The JasperGold family quickly isolates bugs with a fast, static debugging capability, and then proves the absence of bugs, trimming design schedules. For further details on how to ensure guaranteed correctness where it matter most, please visit http://www.jasper-da.com.
Jasper Design Automation, the Jasper Design Automation logo, JasperGold, Formal Testplanner, GamePlan and InFormal are trademarks or registered trademarks of Jasper Design Automation, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.
for Jasper Design Automation
Francine Bacchini, +1-408-839-8153