Solido Design Announces New Transistor-Level Statistical Design and Verification Technology for Analog/Mixed-Signal, Custom Digital and Memory IC Designs

New technology provides framework to ensure that nanometer designs work despite wide variations within a given manufacturing process

SASKATOON, CANADA - February 12, 2007 - Solido Design Automation today took the wraps off a new technology that promises to help designers of analog/mixed-signal, custom digital, and memory integrated circuits (ICs) ensure that their transistor-level designs will work across all manufacturing process variations. Solido, launched in June 2006, has developed new ways to analyze, improve, and verify circuits that heretofore have been costly, difficult, and at times impossible to design.

"Semiconductor companies are suffering because existing design automation technologies and tools lack fundamental capabilities needed for today's nanometer manufacturing processes," said Solido's cofounder and CEO, Amit Gupta. "Solido's goal is to provide a path to success for these companies. Our technology will give semiconductor designers a way to stop over-designing their chips and get them into customers' hands faster than ever before."

Called transistor-level statistical design and verification, the new Solido patent-pending technology leverages statistical process information to make designs robust to process variations. It incorporates such methodologies as statistical sampling, tradeoff analysis, circuit characterization, and circuit enhancement to discover problems and help designers explore opportunities to compensate for those problems. In turn, designs are better able to withstand process variations and meet specifications without being over-designed.

Because statistical design and verification produces enormous volumes of raw data, Solido has also developed new statistical data mining and visualization algorithms that enable designers to identify areas of interest, efficiently explore the data, analyze and interpret it, and prepare reports.

Solido's technology addresses the global and local statistical variations that occur in semiconductor devices designed for manufacturing processes at or below 180 nanometers. Global statistical variations include lot-to-lot and die-to-die manufacturing variations; local statistical variations include device mismatch. Such variations can have a negative impact on manufacturing yield, and can cause circuits to fail altogether. Currently designers have no tools with which to assess the impact of statistical variations; instead, they employ such techniques as Monte Carlo analysis, which provides only the most basic of statistical analysis capabilities and provides no insights into yield-limiting circuit properties, and the interminable tradeoffs required between circuit yield and performance.

According to Gupta, Solido's technology meets the five criteria required for statistical nanometer circuit design, which are the following:
  1. First and foremost, the technology must make no simplifying assumptions. Existing approaches assume far too much, which can lead to significant margins of error.
  2. The technology must support arbitrary statistical models, from the very simple to the very complex, to achieve exacting accuracy requirements.
  3. The technology must scale to industrial-size circuits with their thousands of design, process, and environmental variables with nonlinear mappings to performance and yield.
  4. The technology must make use of industry-standard SPICE-like simulators as well as users' proprietary simulators developed in-house.
  5. The technology must integrate seamlessly into viable CAD environments, making it efficient for designers to use throughout the design process.
The new technology from Solido will be integrated into existing industry-standard analog, mixed-signal, and custom design flows. Solido is currently working with customer partners and will announce its transistor-level statistical design and verification tool suite in the next few months.

About Solido Design Automation
Solido Design Automation Inc. provides transistor-level statistical design and verification software solutions for analog/mixed-signal, custom digital, and memory integrated circuits. Founded by serial analog entrepreneurs, the privately held company is headquartered in Saskatoon, Canada with sales offices in U.S.A.,Japan and Europe. For further information, visit or call 306-382-4100.

Editorial Contact:
PR for Solido Design Automation - Cayenne Communication LLC
Michelle Clancy, 252-940-0981, Email Contact


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