DDR Memory System Specification Wins Coveted DesignVision Award at DesignCon
"I am happy that the efforts and focus of the DFI working group has been recognized by the International Engineering Consortium," said Bryan Jones, IP outsourcing program manager, Mobility Group LTG/DAC for Intel Corporation. "Integrating and verifying memory controller logic and PHY designs signify a substantial cost to all parties involved. From a systems perspective, this DFI specification 1.0 represents a momentum towards creating and sustaining more reusable IP in this space."
The coveted DesignVision Award, in the Interconnect Technologies and Components category, was awarded by John Janowiak, the president of the International Engineering Consortium was accepted, on behalf of the DFI participants, by Bryan Jones, of Intel and Brian Gardner, vice president of IP products at Denali. The DFI specification 1.0 describes a common interface between DDR-DRAM memory controller logic designs and DDR DRAM physical interface (DDR PHY) designs in order to reduce cost, time-to-market, and increase the potential for reuse of the individual components that make up the memory system. A copy of the DFI specification can be accessed at: http://www.ddr-phy.org.
"We are very pleased that our technical achievements have been highlighted in this way," said Brian Gardner, vice president of IP products at Denali. "These companies represent the best minds in the field, and their participation in this industry initiative will enable better DDR solutions."
About the DFI Specification
The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, visit: http://www.ddr-phy.org.
About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND and DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.
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