Altera FPGAs Address Design Challenges at DesignCon 2007


San Jose, Calif., January 24, 2007-

 

What:              High-end FPGAs, structured ASICs, design tools as well as protocol solutions from Altera Corporation (NASDAQ:ALTR) and its partners will beon exhibit at DesignCon 2007. Taking place Jan. 29 to Feb. 1 in Santa Clara, Calif., visitors to Altera’s booth no. 503 will:

  •         Discover how the award-winning 65-nm Stratix® III FPGAs, HardCopy® II structured ASIC family and software design tools deliver the highest performance with the lowest power in the industry.

  •         Witness the industry’s fastest production FPGA serial transceivers operating error free on 1 m of FR-4 backplane and 15 m of PCI Express cable.

  •         See the first demonstration showcasing the interoperability of Altera’s Stratix II GX FPGA, running Sarance Technologies’ Interlaken intellectual property (IP) core which includes five channels at 6.375 Gbps, with Cortina’s CS3477, the market’s highest-density, bandwidth-doubling 10 Gbps Ethernet MAC Aggregator IC.

    Visitors to the conference can also attend technical presentations from Altera and its partners:

     

    Tuesday, January 30th

     

     

    9:20 a.m. – 10:00 a.m.

    Equalization Challenges for 6-Gbps Transceivers Addressed by PELE—A Software-Focused Solution

    Presented by Altera and Mentor Graphics Corporation

    10:15 a.m. – 10:55 a.m.

    Calibration Techniques for High-Bandwidth Source-Synchronous Interfaces

    Presented by Altera

    2:00 p.m. – 2:40 p.m.

    Serial Protocol Compliance of an FPGA-Integrated Mixed-Signal Transceiver

    Presented by Altera

    2:00 p.m. – 2:40 p.m.

    Digitally Assisted Adaptive Equalizer in 90 nm With Wide-Range Support From 2.5 Gbps–6.5 Gbps

    Presented by Altera

    Wednesday, January 31st

     

     

    9:40 a.m. – 10:20 a.m.

    FPGA Design for Signal and Power Integrity

    Presented by Altera

    2:50 p.m. – 3:30 p.m.

    Pre-Emphasis and Equalization Parameter Optimization With Fast, Worst-Case/Multibillion-bit Verification

    Presented by Altera, Mentor Graphics Corporation and Molex Incorporated

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