DFT MAX Reduces Test Data Volume, Enables Higher-Quality Production Testing
"Oki needed a solution to further improve the product quality of our complex systems-on-chips (SoCs), but do so in a cost-effective manner that would allow us to utilize our existing automatic test equipment," said Jiro Kobayashi, senior manager of Oki's Telecom & Automotive System business division in Silicon Solutions Company. "DFT MAX substantially reduced the amount of data needed for our at-speed tests, using a very low area overhead and requiring very little additional design effort to incorporate into our existing DFT flows. For these reasons, Oki has adopted DFT MAX for our future SoC designs."
Very high quality testing can be achieved by applying tests at a chip's operating frequency. But if different circuits operate at different frequencies, it can be a difficult and time-consuming task to design and verify custom logic to control the complex clock sequencing. This was the challenge faced by designers of a several-million-gate Oki communications SoC containing circuits driven by a large number of internal and external clocks operating at different frequencies. Rather than develop a custom clock controller from scratch and risk delaying the project schedule, Oki designers instead used DFT MAX to fully synthesize the clock controller circuits and integrate them into the design. This automated approach saved a significant amount of engineering time and effort, and made it possible to tapeout the design on time. Synopsys' TetraMAX(R) DSMTest automatic test pattern generation (ATPG) solution was later used to generate high-coverage transition delay patterns which were applied successfully on the tester to validate the fabricated device.
"As designs have grown larger and more challenging to test, semiconductor companies such as Oki are turning to Synopsys for the most innovative DFT solutions," said Graham Etchells, director of Test Marketing, Synopsys Implementation Group. "DFT MAX helps these companies achieve their quality goals with minimal impact on design time and silicon cost. And because migration to DFT MAX can be accomplished in days instead of months, our customers quickly see tangible benefits from applying more defect-based tests -- transition delay, bridging, IDDQ, and now small delay defect tests --to achieve even higher test quality and higher diagnostics accuracy."
Using DFT MAX requires no expertise in test compression techniques. Its gates-only adaptive scan architecture is the most area-efficient solution available. By avoiding the use of complex sequential state machines for compression/decompression, the adaptive scan architecture disperses test logic throughout the design, alleviating wire-routing congestion and reducing silicon area overhead cost. Working seamlessly within Synopsys' Galaxy(TM) Design Platform, DFT MAX produces predictable results with little to no impact on timing.
Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at www.synopsys.com.
NOTE: Synopsys and TetraMAX are registered trademarks of Synopsys, Inc. Galaxy is a trademark of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Editorial Contacts: Sheryl Gulizia Synopsys, Inc. 650-584-8635 Email Contact
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