TransEDA Joins Novas Harmony Partner Program and Integrates VN-Property DX with Novas Debussy
LOS GATOS, Calif. (U.S.A.) — June 3, 2002 — TransEDA® PLC, the leader in ready-to-use verification solutions for electronic designs, today announced integration of its VN-Property DX dynamic property checker with Novas Software's Debussy® knowledge-based debug system and support for Novas' open Fast Signal Database (FSDB). TransEDA also announced it has joined the Novas Harmony Partner Program. The partnership of the companies will enable close cooperation to speed design debug in a property-driven verification methodology. VN-Property DX accelerates verification of complex systems from architecture to system level by measuring the effectiveness of simulation against standard or design-specific properties. By integrating VN-Property DX with Debussy, TransEDA enables engineers to decrease the time spent debugging property violations. When an engineer finds properties violated in simulation with VN-Property DX, those violations can be seamlessly and immediately debugged using Debussy.
“TransEDA is pushing toward a property-driven verification methodology for electronics design engineers,” said Scott Sandler, Novas Software's president and CEO. “We believe properties are vital to the future of verification. Debussy gives designers an environment for accessing all their design files and tools, and a productive way to debug and fix designs earlier in the verification process. The integration of dynamic property checking into this process will enable our customers to increase their productivity in a new and extraordinarily valuable way.”
“TransEDA enables engineers to accelerate verification from architecture to system level by specifying design intent with properties and re-using that specification throughout the design process,” said Tom Borgstrom, vice president of marketing at TransEDA. “Novas is the leader in debug productivity tools and we've partnered with them to provide our customers with a best-in-class debug solution for the property-driven verification methodology.”
Enabling Faster Debug in a Property-Driven Verification Flow
VN-Property DX enables engineers to view information about a property's values in either a textual representation or a simple graphical form. After viewing results in VN-Property DX, engineers can then use Debussy for a more detailed investigation such as cross-probing between signals and the RTL source code.
VN-Property DX also supports Novas' FSDB simulation log format as part of its integration with Debussy. Engineers can capture simulation results in an FSDB file and use these results for both simulation debug with Debussy and dynamic property checking with VN-Property DX. This simplifies the simulation flow, eliminating redundant files.
About Verification Navigator
The VN-Property DX dynamic property checker is part of TransEDA's Verification Navigator® integrated design verification environment, which features tools that enable IC designers to manage and shorten verification time. In addition to VN-Property DX, Verification Navigator includes VN-Check configurable HDL checker, VN-Cover coverage analysis, VN-Cover Emulator coverage analysis for hardware-assisted verification, VN-Optimize test suite analysis, and VN-Control application-specific test automation. Verification Navigator supports all leading Verilog, VHDL, and dual-language simulators and is available on the Solaris, HP-UX, AIX, Linux, Windows NT, and Windows 2000 platforms.
Pricing and Availability
VN-Property DX version 2002.07 with support for Novas Debussy and FSDB will be available in July 2002. VN-Property DX and is independent of the simulation language used. Pricing starts at $15,000 (U.S.) for an annual subscription license. For more information on VN-Property DX, visit www.transeda.com/vnpropertydx.
TransEDA PLC (symbol TRA on the London Stock Exchange) develops and markets ready-to-use design verification solutions for electronic field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and system-on-chip (SoC) designs. The company's verification IP library includes models and properties for advanced microprocessors and standard bus interfaces.
TransEDA's design verification software performs application-specific test automation, configurable HDL checking, dynamic property checking, code and finite state machine (FSM) coverage analysis, and test suite analysis. TransEDA's tier-one customers include 18 of the world's top 20 semiconductor vendors.
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