Cypress Deploys Synopsys PrimeRail to Speed Tapeout of Mobile Phone IC Design

Synopsys Galaxy Design Platform and PrimeRail Deliver Complete Flow for Multi-threshold CMOS Design

MOUNTAIN VIEW, Calif., Dec. 4 /PRNewswire-FirstCall/ -- Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Cypress Semiconductor Corp. has successfully taped out its West Bridge(TM) Antioch(TM) peripheral controller multimedia 3G/3.5G mobile phone integrated circuit (IC) using the Synopsys Galaxy(TM) design platform RTL-to- GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multithreshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enabled peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation.

"For our mobile phone chip design, we needed a solution that could address peak current problems related to the use of Power Gating switches," said Nagendra Cherukupalli, vice president of Asia Pacific design centers and chip integration at Cypress. "Synopsys' PrimeRail and its integration with the Galaxy design platform enabled our designers to analyze power integrity issues of the power gating switches and decoupling capacitors prior to tapeout."

Built on Synopsys' gold-standard Star-RCXT(TM) extraction and PrimeTime(R) sign-off technologies, PrimeRail offers full-chip analysis, dynamic memory and macro-modeling capabilities for advanced multi-voltage, low-power, high- performance designs. Its multimode analysis capability enables users to pinpoint and mitigate problems with critical power-up rush current or excessive current during wake-up to active mode in MTCMOS designs. PrimeRail is integrated with the Galaxy design platform, allowing designers to predict voltage drop during floorplanning, perform pre- and post-layout analysis with on-chip decoupling capacitance, and achieve full-chip sign-off with package parasitics.

"Cypress has once again placed their confidence in Synopsys' comprehensive low-power solution," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "PrimeRail's analysis capabilities are an extension of our low-power leadership, and the power network solution is the latest in our efforts to constantly strengthen Synopsys offerings. The Cypress project demonstrates our commitment to addressing the growing challenges designers face with low-power design, particularly in the areas of mobile and wireless applications."

Cypress is a leader in high-performance silicon solutions for consumer, computation, and data communications applications.

About Synopsys

Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at www.synopsys.com .

NOTE: Synopsys and PrimeTime are registered trademarks of Synopsys, Inc. Galaxy and Star-RCXT are trademarks of Synopsys, Inc. Any other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

    Editorial Contact:
     Sheryl Gulizia
     Synopsys, Inc.
     650-584-8635
     
Email Contact

Web site: http://www.synopsys.com//




Review Article Be the first to review this article
CST: Webinar November 9, 2017

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Teklatech: Work smart, Not hard
More Editorial  
Jobs
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
ARM TechCon 2017 at Santa Clara Convention Center Santa Clara CA - Oct 24 - 26, 2017
MIPI DevCon Bangalore 2017 at The Leela Palace Bengaluru India - Oct 27, 2017
The 2017 International Test Conference at Fort Worth Convention Center Fort Worth TX - Oct 31 - 2, 2017
MIPI DevCon Hsinchu City 2017 at Sheraton Hsinchu Hotel Taiwan - Oct 31, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise