The HDL Explorer tool within the ispLEVER suite integrates design creation, analysis, verification and documentation in a customizable HDL analysis environment. The HDL Explorer tool generates graphic representations of a design's hierarchical structure and connectivity based on the source HDL, and is used for IP integration, design maintenance and re-engineering of complex FPGA HDL designs. The HDL Explorer tool helps designers visualize higher-level abstractions of the design structure, reducing the time required for design management and documentation. The HDL Explorer tool also helps designers produce high-quality code with "linting" technology to detect common design rule faults.
Chris Fanning, corporate vice president of software and IP solutions, said: "Verific's HDL Component Software is a comprehensive tool that Lattice has leveraged in its development of our HDL Explorer tool, a significant new capability that enables FPGA designers to more effectively and quickly complete their designs."
"Lattice's ispLEVER design tool suite is noted for its ease of use, flexibility and performance," said Rob Dekker, Verific's president. "We're delighted to be part of a tool suite that so effectively serves the programmable logic designer community."
Verific's HDL Component Software is written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. All products are licensed as source code and come with online support and maintenance.
About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry's broadest range of Programmable Logic Devices (PLD), including Field Programmable Gate Arrays (FPGA), Complex Programmable Logic Devices (CPLD), Mixed-Signal Power Management and Clock Generation Devices, and industry-leading SERDES products.
Lattice continues to deliver "More of the Best" to its customers with comprehensive solutions for system design, including an unequaled portfolio of high-performance, non-volatile and low-cost FPGAs.
Lattice's ispLEVER 6.1 adds new design resources and productivity enhancement tools for designers, including the innovative HDL Explorer tool that helps manage and analyze large FPGA designs. The ispLEVER 6.1 release supports Lattice's latest FPGAs, including the new LatticeECP2M(TM) FPGA family, the new LatticeMico32(TM) System for 32-bit microprocessor design and enhanced third-party synthesis and simulation tools.
Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. For more information, visit http://www.latticesemi.com.
About Verific Design Automation
Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog and VHDL front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: firstname.lastname@example.org. Website: http://www.verific.com.
Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.
Public Relations for Verific
Nanette Collins, 617-437-1822