A major issue faced by SoC design teams adopting 90nm and 65nm process nodes is the increase in yield fall out. At 90nm it is estimated that 30% of yield fall out is due to performance and signal integrity issues. As a result, accurate and cost effective at-speed manufacturing test and characterization has become evermore critical to achieve high quality silicon. Traditional at-speed test approaches have proven inaccurate in identifying subtle performance issues, resulting in potential test escapes or overly optimistic device performance characterization.
ScanBurst is a new and innovative at-speed DFT (Design-for-Test) tool from LogicVision designed specifically to overcome the limitations of traditional at-speed DFT techniques. ScanBurst is designed specifically to complement existing ATPG based DFT techniques by providing an environment to easily insert scan and clock control structures for at-speed testing based on LogicVision's patented BurstMode Timing(TM) technology. ScanBurst is integrated with Mentor's FastScan ATPG and TestKompress embedded compression products, and provides a seamless solution that fits within existing scan- based DFT flows.
"The focus on quality of test, especially through the use of an at-speed test methodology, is mission critical for nanometer design," stated Robert Hum, vice president and general manager of Mentor Graphics Design Verification and Test division. "With Mentor's best-in-class ATPG and compression technology, we are able to team with LogicVision, leverage their unique technology, and provide a substantial competitive advantage for our mutual customers."
"Our customers have told us that they want to take advantage of our proven BurstMode technology in our ETLogic(TM) Logic BIST solution within their existing Mentor scan ATPG environment," said Jim Healy president and CEO of LogicVision. "By delivering our at-speed solution in a Scan ATPG environment with Mentor Graphics, we're addressing an unfulfilled need in the market place and helping our joint customers improve their silicon performance characterization and final product quality."
About the BurstMode Timing Technology
The traditional approach of testing for performance related defects with ATPG based solutions has been to generate patterns that target transition delay faults. These patterns are applied using two at-speed functional clock cycles to create a "launch" and "capture" sequence. This approach is often referred to as "double-capture" timing. However, the "double-capture" technique often does not correlate well with functional performance resulting in test escapes or yield loss. In particular it has suffered from what is referred to as "clock stretching." This phenomenon is caused by the instantaneous drain on power rails during the launch and capture cycles that results in an increase of the clock period, and in an optimistic performance rating of the device, as well as reduced delay fault detection. The BurstMode Timing technology avoids this situation by providing for programmable ramping of the at-speed clock activity before each test capture. This ensures that the power rails have recovered from the initial instantaneous voltage drop (no clock stretching) and true functional performance parameters are tested.
BurstMode Timing is a proven technology that has been in production use at leading semiconductor companies as part of LogicVision's Logic BIST solution.
About the ScanBurst Product
ScanBurst provides comprehensive design automation for generating and integrating the on-chip distributed clock and scan control logic, which enables the application of BurstMode Timing in conjunction with Mentor's FastScan and TestKompress ATPG products. ScanBurst also enables users to easily and efficiently apply scan patterns in a truly hierarchical fashion. LogicVision's patented core-isolation-logic greatly simplifies and optimizes the generation and application of scan patterns to individual cores. This provides several significant benefits including reduced test generation times, robust pattern generation and reduced test pattern data volume. The core isolation technology also enables DFT teams to apply at-speed scan patterns to an arbitrary number of cores, allowing them to trade-off test time with average power levels during test. This capability provides significant advantages when dealing with designs that use elaborate clock-gating schemes to achieve low power consumption.
About Mentor Graphics Design-for-Test Tools
Mentor Graphics provides the industry's broadest portfolio of DFT solutions for today's System-on-Chip and deep submicron designs, including integrated solutions for scan, ATPG, EDT, advanced memory test, boundary scan, logic built-in self-test and a variety of DFT-related flows. For more information visit http://www.mentor.com/products/dft
ScanBurst integrated with Mentor's FastScan and TestKompress tools is available for early customer evaluation immediately. Full customer availability is scheduled for Q1 of 2007.
About LogicVision, Inc.
LogicVision, Inc. provides unique test and yield learning solutions in the design for manufacturing space. These capabilities enable its customers, leading semiconductor companies, to more quickly and efficiently learn to improve product yields. The company's advanced Design for Test (DFT) product line, ETCreate, works together with ETAccess and SiVision yield learning applications to improve profit margins by reducing device field returns, reducing test costs, and accelerating both time to market and time to yield. LogicVision solutions are used in the development of semiconductor ICs for products ranging from digital consumer goods to wireless communications devices and satellite systems. LogicVision was founded in 1992 and is headquartered in San Jose, Calif. For more information visit us at http://www.logicvision.com.
Forward Looking Statements
Except for the historical information contained herein, the matters set forth in this press release, including statements as to the expected benefits of the ScanBurst product and partnering with Mentor Graphics are forward- looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. These forward-looking statements are subject to risks and uncertainties that could cause actual results to differ materially, including, but not limited to, the impact of competing products and technological advances, the risk that the expected benefits of partnering with Mentor Graphics and its technologies are not realized, and other risks detailed in LogicVision's Form 10-Q for the quarter ended June 30, 2006, and from time to time in LogicVision's SEC reports. These forward-looking statements speak only as of the date hereof. LogicVision disclaims any obligation to update these forward-looking statements.
Web site: http://www.logicvision.com/