Atrenta Announces Standardization on its Early Design Closure Solution By STMicroelectronics
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Atrenta Announces Standardization on its Early Design Closure Solution By STMicroelectronics

A Company-Wide Deployment Advances ST's Front-to-Back Methodology

SAN JOSE, Calif., July 20, 2006- Atrenta, the leading provider of broad-based design analysis solutions based on industry standard SpyGlass™ technology today announced that STMicroelectronics (NYSE: STM) has standardized on Atrenta's early design closure solution as part of a company-wide front-to-back design methodology.

The deployment of Atrenta's solution at ST, a global semiconductor giant, includes the complete Spyglass solution, together with the ST Design Convention best practices.

"Our fruitful relationship with Atrenta started a few years ago to first address our need for timing constraint screening capabilities. We initially viewed correct and optimal constraint files as mandatory for guiding synthesis, static timing analysis and back-end tools in order to develop high-performance ASICs and SoCs," said Philippe Magarshack, Vice-President Central CAD & Design Solutions of ST's Front-End Technology and Manufacturing Group. "We then extended our relationship to encompass the wide spectrum of RTL analysis capabilities available at Atrenta, including DFT, clock-reset, low power and ST design conventions. We saw particular value in being able to leverage this large set of capabilities within our design community thanks to using it as a single platform. After thorough testing and pilot use, Atrenta's SpyGlass solution is now being deployed throughout our company to improve the productivity of our designers, the quality of their output and the information to design management. We look forward to making Atrenta's technology the backbone of our company's RTL signoff kit."

"Working closely with ST experts has allowed us to develop a signoff quality timing constraints screening product, thanks to ST's deep understanding of designing advanced ASICs and SoC's" stated Dr. Ajoy Bose, Atrenta's chairman, president and CEO. "After focusing on timing constraints screening, we combined our unique predictive development technology with ST's chip design knowledge to deliver a new and enhanced platform that offers an automated way of analyzing various design issues at RT-level and throughout the process, thus smoothing handoff between various design teams, accelerating the design process, and improving overall quality of the designs. We are proud that ST is now deploying our platform throughout its many design teams and design sites worldwide."

Atrenta's solution enhances existing tool flows to take the uncertainty and chance out of electronic development. It turns development into a precise, manageable process, thereby enabling electronics companies to turn out better products, on schedule and on budget.

About Atrenta
Atrenta is the leading provider of broad-based design analysis solutions based on industry standard SpyGlass™ technology. Atrenta's design analysis tools deliver early design closure by eliminating downstream design problems and iterative discoveries. This leads to improved predictability and efficiency in SoC design phases including RTL design, IP reuse, Verification, logical and physical implementation. Atrenta has over 100 customers including the world's top 10 semiconductor companies. Think Early Design Closure, Think Atrenta! For more info, please visit www.atrenta.com.

For more info, please contact:

Corporate:
Krishna Uppuluri, Corporate Marketing
Tel: +1-408-453-3333
Email: Email Contact

Europe:
Bruno Geldreich
Tel: + 33 (0)1 60 11 62 26, Mobile: + 33 (0)6 87 70 87 89,
Email: Email Contact

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.

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