EDA Editors and Technical Editors
Nevada--(BUSINESS WIRE)--April 22, 2002-Alatek, Inc. introduces the industry first LINUX hardware acceleration platform. HES 2.0 (Hardware Embedded Simulation) design platform for Linux, which can speed-up any HDL software simulators from 10X to 100X, without modifications to the current design flow. HES is an "add-on" product to popular HDL simulators and customers' existing HDL design environments. HES works directly with software simulators through PLI, VHPI and other interfaces.
HES 2.0 for Linux is compatible with Redhat 7.2 and Xilinx ISE 4.2 for Linux. HES 2.0 for LINUX includes, HES 2.0 accelerator(s) board and DVM (Design Verification Manager) software. HES supports large ASIC and SoC designs with capacities up to 13 million ASIC gates. The DVM software operates in semi-automatic manner and prepares HDL and EDIF based designs for simulation acceleration. The user can accelerate the entire designs or selected sections of the design by loading them into HES 2.0 accelerator(s) under DVM control. Simulation results may be viewed in the customer's own HDL software simulator. The DVM software is able to accelerate designs made in mixed languages, including VHDL, Verilog, IP Cores and EDIF netlists. Its operation is based on IDP (Incremental Design Prototyping) patented technology, used on all HES products. HES 2.0 series is a "cross-platform" product and can be used with LINUX, UNIX, and NT systems. However, the LINUX system provides the highest design acceleration as compared to other operating systems.
- Simulator speed up 10X - 100X
- No new EDA tools needed
- Expandable, Up-gradable
Pricing and Availability
HES 2.0 Hardware Acceleration products are available now, with pricing as low as $30,000 US Dollars. For more information, visit www.alatek.com for sales locations.
Alatek, Inc. incorporated in 1996 and is headquartered in Nevada. Alatek is privately owned with four corporate offices and research centers in the United States and Europe. Alatek offers innovative design verification solutions, which are complimentary add-ons to the customers' existing design environments and EDA tools. Alatek specializes in the development of Hardware/Software co-design tools, hardware accelerators, intellectual property (IP) cores and other technologies. Having broad expertise in design simulation and verification, particularly for Altera and Xilinx FPGA/CPLD devices, Alatek operates as a full-service design house. Corporate headquarters are located at 3753 Howard Hughes Pkwy, Suite 200-2018, Las Vegas, NV 89109. For additional information, visit Alatek corporate website at www.alatek.com.
HES, IDP, and DVM are trademarks of Alatek, Inc. All other company or product names are the registered trademarks or trademarks of their respective owners.
Lori Swenson, 1-702-892-3720, NV, Marketing and Media Relations