Jasper Design Automation Integrates Verific's SystemVerilog Component Software With JasperGold Verification System

Formal Verification Supplier Commends Verific's Responsiveness, Commitment to Jasper's Success

Alameda, Calif. -- August 31, 2006 -- Verific Design Automation today announced that Jasper Design Automation, provider of breakthrough high-level formal verification solutions, has successfully integrated Verific's SystemVerilog Component Software with JasperGold® Verification System.

"Verific is a superior business partner and we commend them for being responsive and committed to the current market success of JasperGold Verification System," notes Claudionor Coelho, vice president of engineering at Jasper Design Automation. "Without Verific, an internal SystemVerilog development effort would have been a long, difficult process. Verific's language solutions, combined with Jasper's leading assertion synthesis technology, have contributed to our leading position in formal verification for standard assertion and design languages."

"Jasper is a highly valued partner, and following on to our close collaboration on PSL, we are excited to work with them on the SystemVerilog solution" says Verific's president, Rob Dekker. "We have built a long-standing relationship with Jasper, delivering a variety of HDL component software packages for JasperGold Verification System."

In addition to SystemVerilog component software, Verific offers a number of other hardware description language (HDL) component software packages, all written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. Products include SystemVerilog, VHDL and Verilog parsers, analyzers, and elaborators, as well as a register transfer level (RTL) database. All products are licensed as source code and come with online support and maintenance.

About Verific Design Automation
Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog and VHDL front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: http://www.verific.com.

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For more information, contact:
Nanette Collins
Public Relations for Verific
(617) 437-1822
Email Contact


JasperGold is a registered trademark of Jasper Design Automation. Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

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