Verific Adds Liga Systems to Growing Customer List; Verific HDL Component Software Serves as RTL Front End to Liga Systems' New Hybrid Simulator

ALAMEDA, Calif.—(BUSINESS WIRE)—July 18, 2006— Electronic Design Automation (EDA) newcomer Liga Systems Inc. announced today that Verific Design Automation's hardware description level (HDL) Component Software will serve as the register transfer level (RTL) front end for NitroSIM(TM), its Hybrid Simulator.

Liga Systems, an EDA company focused on delivering lightning-fast RTL simulation to the desktop, has integrated Verific's Verilog parser, analyzer and elaborator with its Hybrid Simulator. Verific's HDL component software packages, which include an RTL database, are written in platform-independent C++ that compiles on Solaris, HP-UX, Linux and Windows platforms. All products are licensed as source code and come with online support and maintenance.

"Liga Systems turned to Verific for its industry-leading HDL Component Software because it helped us save invaluable time and effort," says Henry Verheyen, Liga Systems' chief executive officer. "Our team has found the Verific code to be very clear, providing good value as we extend its use for simulation. Using Verific's front-end technology, we were able to bring up a complex Verilog RTL compiler quickly, reducing our time to market, while achieving a high quality product."

"It gives us great pleasure to work with Liga Systems as it brings its first product to market," adds Michiel Ligthart, Verific's chief operating officer.

Verific's entire line of HDL Component Software will be demonstrated in Booth #3345 during the 43rd Design Automation Conference (DAC) July 24-27 at San Francisco's Moscone Center.

To schedule a demonstration during DAC, visit Verific's website located at: Or, contact Rick Carlson, Verific's vice president of sales. He can be reached at (970) 946-1755 or via email at

About Verific Design Automation

Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker It develops and sells C++ source code-based SystemVerilog, Verilog, VHDL and PSL/Sugar front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Website:

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

Public Relations for Verific
Nanette Collins, 617-437-1822

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