New Litho-Driven Detailed Routing Technology With Embedded Variation and Timing Optimization Results in Fastest Path to High-Yield Design ClosureSANTA CLARA, Calif.—(BUSINESS WIRE)—July 17, 2006— Sierra Design Automation, Inc., the technology leader in variability-driven IC implementation solutions, today introduced Olympus-SoC(TM), an IC implementation system that bridges the gap between design and manufacturing environments. Olympus-SoC is a next-generation netlist-to-GDSII system that addresses lithography variation and timing closure in the highest capacity IC implementation architecture in the industry today. Olympus-SoC builds upon Sierra's ground-breaking Design-for-Variability solution, Sierra Pinnacle(TM), and extends it with litho-driven detailed routing technology. This solution is targeted for high-end customers in wireless, handheld, graphics, set-top boxes, networking and processor application segments who are designing at 65nm and below processes. The company also disclosed that the product is currently in controlled availability at early partner sites with general availability later this year.
Challenges facing IC implementation at 65nm and 45nm process nodes
With early 65nm chips heading towards production and test chip trials at 45nm under-way, three critical design challenges have emerged:
-- Lithography-aware physical implementation
-- Variation-based Timing Closure (a.k.a. Design for Variability or Multi-Mode Multi-Corner)
-- Physical Design Capacity
At 65nm process nodes and below, one of the biggest factors affecting yield is lithography variations. There is increasing distortion in the printed patterns vis-a-vis the intended structures in the layout database. This problem manifests itself in the form of manufacturing faults such as bridging, pinching and via failures. There is increasing usage of OPC simulation and RET to address this challenge. However, with 65nm and 45nm nodes, the number of errors is too large and the problem becomes intractable to be fixed just in the manufacturing stage. Further, litho-related layout modifications done in isolation of design metrics, such as timing and variation, could result in performance degradation and timing-related chip failures.
Design for Variability (DFV) refers to the analysis and implementation of a design for various design contexts and timing variations due to device/interconnect scaling. Current-generation implementation systems were never architected to handle this problem in a true concurrent manner. The solution demands a scalable analysis architecture that can accommodate an arbitrary number of timing graphs represented concurrently to represent each variation scenario. Any approximations, like merging constraints over design modes or merging process corners, result in significant loss of accuracy impacting design yield, timing closure and time-to-market. In absence of such capabilities, designers have to iterate unpredictably in sign-off ECO loops, add pessimistic margins which produce designs with larger area and power dissipation and lower yields.
With the rapid growth in design sizes, designers are moving to larger block sizes in hierarchical flows. In addition, flat physical design flows are being applied to reduce die-area and cost, where applicable. It is imperative that a very high capacity physical implementation architecture be available which can address a flexibility of design styles -- flat, hierarchical or some hybrid of the two. In conjunction with Design for Variability, there can be a significant explosion of data that needs to be carefully designed for. Also, Chip Assembly flows are gaining traction as hierarchical designs have to achieve top-level design closure over multiple blocks.
Sierra Olympus-SoC(TM) -- Next Generation IC Implementation System
Olympus-SoC(TM) is a complete IC implementation offering from Sierra Design Automation targeted at 65nm/45nm designs. It augments Sierra Pinnacle(TM), the industry's leading Design for Variability solution. Olympus-SoC is a netlist-to-GDSII system with the highest capacity implementation architecture, native sign-off quality timer with patented virtual timing graph technology and best-in-class physical implementation engines. Olympus-SoC allows designers to account for design, process and lithography variation throughout the IC design flow. Integral to Olympus-SOC is Sierra's next-generation detailed routing architecture which embeds variation-aware timing, optimization and litho-modeling to address OPC/RET effects early in the design cycle and ensure faster timing closure for complex process rules of 65nm and below. Some of the technology highlights include:
-- Litho Driven Routing - A fully featured, multi-CPU detailed routing engine built ground-up to address complex 65nm DRC rules and litho-errors. Unlike pure gridded or pure gridless routing methods of traditional routing solutions, Olympus-SoC's "hybrid" approach obtains the speed of gridded routers with the accuracy of gridless approaches. Dynamic polygonal shape update of objects during routing ensures full 65nm support. At the core of the routing engine is a 65nm/45nm shape-based multi-CPU DRC engine that evaluates complex shape-based DRCs as it routes. It avoids notches and other types of post-processing completely to produce inherently more litho-friendly designs. Techniques such as wire spreading, redundant via insertion, jog-widening and timing driven metal fill are also available. The architecture also includes support for Critical Area Analysis to account for random process variations.
-- Unique OptRoute Technology - The OptRoute engine in Olympus-SoC is the algorithmic cockpit that enables "live" interaction between route-based variability optimization and detailed routing. OptRoute ensures that both the engines are constantly in-sync with the changes being made to the design and are driven by the same embedded signoff variation-aware timing engine to achieve timing closure across all modes and corners during routing.
-- Powerful ECO Routing - Olympus-SoC offers multi-CPU ECO routing built-in with post-route optimization to achieve rapid timing closure. In addition, Olympus-SoC corrects lithography hot-spots and litho-unfriendly structures to guide the router to make changes to the design layout. These are fixed without affecting the overall timing performance and OCV-related hold violations with customized routing techniques including wire-widening and local re-routing.
-- Sign-off Quality Timer - The embedded, signoff variation-aware timing engine drives the router and optimization engine to automatically achieve timing closure across all modes and corners while routing. The analysis engines also support modeling for Metal thickness variation due to CMP (Chemical Mechanical Polishing).
"Today, many of the top-20 semiconductor houses are standardizing on Sierra Pinnacle for variation-based timing closure," said Pravin Madhani, President and CEO, Sierra Design Automation, Inc. "Olympus-SoC builds upon Sierra's ground-breaking architecture to deliver the industry's first variation and litho-driven netlist-to-GDSII IC implementation system. With our OptRoute technology, we have achieved an unprecedented level of unification between litho-driven routing and timing optimization that enable rapid high-yield design closure. Unlike current offerings in the market, Sierra Olympus-SoC is the only implementation system built ground-up to address the gap between design and manufacturing."
Pricing and Availability
Sierra Olympus-SoC is available immediately with prices beginning at $995,000 U.S. list for a one-year license.
About Sierra Design Automation and Sierra Olympus-SoC
Sierra Design Automation is a privately funded EDA company founded in January 2003. The Company's world-class EDA team is focused on providing semiconductor designers with innovative IC implementation solutions that comprehensively address the performance, capacity, time-to-market, and variability challenges occurring at the 65nm, 45nm, and below process nodes. Olympus-SoC, Sierra's flagship product, provides the next generation place and route system that concurrently addresses variations in lithography, process corners and design modes. It is built on Sierra Pinnacle, the customer proven and industry leading design for variability physical implementation solution. Technology highlights include lithography driven detailed router, embedded signoff quality timing engine, adaptive variability engine in addition to an open architecture and ultra-compact database that can handle extremely large capacities. For further information visit: www.sierra-da.com .