Denali Opens Register Description Language, Announces SystemRDL
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Denali Opens Register Description Language, Announces SystemRDL

SystemRDL Provides Hardware, Software Developers With Standard for Specifying, Managing Registers

PALO ALTO, Calif., May 30 /PRNewswire/ -- Denali today announced the production release of the SystemRDL(TM) language specification and said that any company can now obtain the SystemRDL specification without paying royalties or license fees. The specification is available online at:

SystemRDL replaces the former RDL language specification and includes numerous extensions and enhancements to enable hardware designers and software developers with a common language for describing and managing control registers for system-on-chip (SoC) development.

"We are pleased with the support we've received from our customers and partners to enhance and extend the original RDL language in a meaningful way," says Mark Gogolewski, Denali's chief technology officer. "SystemRDL addresses a critical element of SoC design with the appropriate language for describing and managing registers that bridges the disciplines of hardware design, verification, and software development. By opening the language specification, we are accelerating the ecosystem and enabling more companies to benefit from the standard."

Configuration registers exist in all semiconductor chips and intellectual property (IP) products, often numbering in the thousands. These registers store key data that define the chip's operation, and usually represent the largest portion of the chip specification or programmers guide.

"Modern engineering methodologies are changing about as fast as chip densities, and anything that offers significant improvements in chip development efficiency is a good thing," remarks Pete LaFauci, senior principal design engineer at AMCC. "SystemRDL is the answer to bridging the gap between our chip designers, verifiers, software engineers, and end customers. With a standard description language and an object-oriented approach, common register specification and 'true' reuse is not only a reality but achievable by design."

SystemRDL is used to describe the details of register structures and operation, enabling automatic generation of synthesizable register code, models, documentation and other specialized views for internal hardware design and software development. This eliminates manual and error-prone processes of developing registers and maintaining consistent and accurate views across diverse teams involved in system designs.

Comments Jonathan Michelson, author of "The Art of Verification with SystemVerilog Assertions": "SystemRDL is a robust language that addresses a critical need in SoC design today. The ability to specify control registers at a higher level of abstraction is very powerful, and integrates well with emerging SystemVerilog methodologies for SoC design and verification."

The language is also supported by founding members of the RDL Alliance announced earlier this year, which is also being renamed as the SystemRDL Alliance. Founding members include Denali Software, Mentor Graphics, MIPS and Rambus. These and other partners share a common goal in promoting the standard use of SystemRDL in the development and delivery of IP used in SoC designs. Using SystemRDL to automate the generation of all necessary register views enables significant productivity gains in IP design and integration efficiency, and increases overall quality through a correct-by-construction methodology.

"Cadence is very supportive of open standards that benefit the design community at large," affirms Victor Berman, group director for language standards at Cadence. "SystemRDL in particular addresses a key need to enable more efficient design interaction between hardware and software developers. We applaud Denali's choice to open the SystemRDL language specification, and we look forward to participating in future standardization efforts."

Bill Martin, general manager of Mentor Graphics IP division, adds: "Using standards is critical to developing and supporting high quality, reusable IP for our customers. Using SystemRDL as part of our IP specification and creation process, along with the XML IP databook provided by The SPIRIT Consortium, means that our IP can be quickly and reliably deployed and integrated into our customer designs."

Denali is working with partners and customers to move the SystemRDL language toward an industry standards body. For more information about SystemRDL, or how to join the SystemRDL Alliance, visit:

About Denali Software

Denali Software Inc. is the world's leading provider of Electronic Design Automation (EDA) and Intellectual Property (IP) products for design and verification of semiconductor chip interfaces. Denali's Databahn(TM) products provide optimal control and data throughput for external DRAM and Flash memory devices. Spectra(TM) is a fully featured flash file system for NAND and NOR memory systems. PureSpec(TM) and MMAV(TM) verification IP products support all standard interfaces, including DRAM, Flash, PCI Express, ASI, AMBA, USB, Ethernet, Serial ATA, and CE-ATA. Denali's Blueprint(TM) SystemRDL compiler provides a complete solution for on-chip register design and management. For more information, visit Denali at, call (650) 461-7200 or email Email Contact.

The Denali logo, Denali, Blueprint, Databahn, Dataplex, MMAV, PureSpec, Spectra, and SystemRDL are trademarks of Denali Software Inc. All other trademarks are the property of their respective owners.

    For more information, contact:
    Nanette Collins                               Kevin Silver
    Public Relations for Denali Software Inc.     Denali Software Inc.
    617-437-1822                                  650-283-3488
Email Contact                               
Email Contact

CONTACT: Public Relations, Nanette Collins, +1-617-437-1822, or
Email Contact, for Denali Software Inc.; or Kevin Silver of Denali
Software Inc., +1-650-283-3488, or Email Contact

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