LogicVision Announces the Industry's First True At-Speed Deterministic Test Compression Solution

ETCompression offers unparalleled flexibility, quality and test cost savings

SAN JOSE, Calif., May 23 /PRNewswire-FirstCall/ -- LogicVision, Inc. (NASDAQ: LGVN), a leading provider of yield learning solutions, today announced the availability of ETCompression, a deterministic test compression solution, targeted at chips designed at advanced nanometer scale technology nodes. ETCompression provides the first true at-speed launch-on-shift test application using LogicVision's patent pending Burst-Mode(TM) test timing architecture. This provides both very high transition fault coverage as well as signal integrity screening through run-time control of internal scan rates and functional clock cycle spreading.

At-speed testing has become a requirement for designers of today's highly integrated circuits, as semiconductor manufacturers are faced with increasingly subtle defect mechanisms and new process-design interactions, resulting in an increasing number of performance and quality issues. ETCompression provides the unique ability to test chips at-speed, under conditions which simulate actual functional operation, and does so with substantial test time and test data volume reductions. The result is an unmatched level of coverage and quality, at a lower test cost.

ETCompression builds upon LogicVision's industry leading embedded logic test solutions, including a hierarchical architecture that provides both high scalability and full core reuse leading to significant integration efficiencies and time-to-market savings. ETCompression can be used purely with compressed deterministic scan patterns, or be seamlessly complemented with the application of pseudo-random patterns to achieve the highest quality levels required in communication, consumer, storage and automotive devices.

    Tool capabilities include:
    * Over 10x test time and 100x test data volume reduction.
    * Patent pending Burst-Mode(TM) test timing architecture for true at-speed
      test application and run-time programmable power management and
      characterization.
    * IEEE 1500 compliant distributed test access architecture and patented
      core Shared Isolation for hierarchical test integration for minimizing
      area overhead and performance impact.
    * Automated RT level test analysis, generation and insertion flow  for
      fast test integration, including handling of unknowns, and automated
      fixing of violations.
    * Full physical design flow integration, including automated generation of
      design constraints, synthesis scripts, timing analysis, formal
      verification and testbench generation.

"At advanced process nodes the industry needs to maintain test quality and good yields while containing test costs in order to remain competitive," said Jim Healy, president and CEO of LogicVision. "Testing chips under functional conditions is essential to ensure ultimate product quality, and ETCompression offers this key capability, allowing users to execute a comprehensive SoC test plan efficiently while controlling costs."

Pricing and availability

ETCompression is available immediately, and will be on display at the upcoming Design Automation Conference, July 24-28 in San Francisco, California. ETCompression works seamlessly with other LogicVision tools and is interoperable with all major physical design flows, including Cadence Design Systems, Magma Design Automation, and Synopsys.

About LogicVision Design-for-Test Tools

LogicVision is the market leader in Built-In-Self-Test (BIST) solutions, with a comprehensive suite of advanced embedded test capabilities, including ATPG, memory, logic, boundary-scan, SerDes, PLL and board-level solutions. Central to LogicVision's offering is a powerful RT-level automation flow that ensures easy and successful integration of embedded test capabilities with minimal impact to the design flow and schedule.

About LogicVision, Inc.

LogicVision, Inc. provides unique yield learning capabilities in the design for manufacturing space. These capabilities enable its customers, leading semiconductor companies, to more quickly and efficiently learn to improve product yields. The company's advanced Design for Test (DFT) product line, ETCreate, works together with ETAccess and SiVision yield learning applications to improve profit margins by reducing device field returns, reducing test costs, and accelerating both time to market and time to yield. LogicVision solutions are used in the development of semiconductor ICs for products ranging from digital consumer goods to wireless communications devices and satellite systems. LogicVision was founded in 1992 and is headquartered in San Jose, Calif. For more information visit http://www.logicvision.com .

Forward Looking Statements

Except for the historical information contained herein, the matters set forth in this press release, including statements as to the expected features and benefits of the ETCompression product, are forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. These forward-looking statements are subject to risks and uncertainties that could cause actual results to differ materially, including, but not limited to, the impact of competitive products and technological advances, the risk that the product will not lead to the benefits that were expected by LogicVision, and other risks detailed in Form 10-Q for the quarter ended March 31, 20065, and from time to time in LogicVision's SEC reports. These forward-looking statements speak only as of the date hereof. LogicVision disclaims any obligation to update these forward-looking statements.

CONTACT: Kirsten McMullen of LogicVision, Inc., +1-408-453-0146,
Email Contact

Web site: http://www.logicvision.com/




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