Ponte Solutions Releases Yield Analyzer Version 2.0; The Production-Proven Design-Stage Yield Analysis Tool Now Ready for Proliferation

MOUNTAIN VIEW, Calif.—(BUSINESS WIRE)—March 29, 2006— Ponte Solutions, Inc., the design-for-yield company, announced the availability of Yield Analyzer(TM) v2.0, featuring a unique model-based analysis technology providing automated yield analysis and enabling optimization of a design prior to its tape-out. Yield Analyzer reduces manufacturing cost and time-to-volume production of complex semiconductor ICs by revealing yield-sensitive areas of the design and enabling yield improvement at the design stage, prior to committing to expensive fabrication.

Yield Analyzer has been validated and is already in use at IDMs, foundries and fabless IC design companies manufacturing high volume products around the world.

"With 90nm technology in the mainstream and 65nm technology readily available, yield, in addition to area, timing and power, has become a major concern for designers," said Alex Alexanian, president and CEO of Ponte Solutions. "Ponte anticipated this trend more than two years ago and has worked with technology partners to develop and validate the accuracy, usability and performance of Yield Analyzer as design-stage yield characterization and analysis tool."

With each successive process generation, product yield has become progressively lower. Analysts predict that, without a change in design methods, yields of 65nm designs will stay low and unpredictable. One reason is that designers and manufacturing groups have traditionally relied on design rules as an abstraction of process information. If the designers follow these rules, the manufacturing process should produce an acceptable yield. However, with 130nm and smaller process nodes, this approach began to break down; two different designs that are fully DRC clean, i.e. they both meet the design rules without any violations, result in considerably different manufacturing yield. Lack of visibility into yield problems at the design stage has become the main problem of IC manufacturing at sub-130nm geometries.

Ponte's model-based approach solves the impending yield crisis while leveraging existing design flows. Ponte's Yield Analyzer addresses this issue effectively at every step of the design flow starting from library/IP design and characterization to netlist generation, floorplanning, full chip detailed routing and ECO. Now, designers can analyze the yield sensitivities of their libraries, IPs or full chip designs, in an evolutionary design methodology. Thus, adding yield as the fourth dimension to their design goals, besides area, timing and power.

Core technologies in the foundation of Yield Analyzer v2.0 include:

-- Unified yield modeling platform that allows integrated approach to yield analysis during design stage;

-- Proprietary third-generation analytical engines for critical area extraction- enables highest possible accuracy to cover all intricacies of nanometer technologies and avoids accuracy loss due to commonly used sampling techniques;

-- Infrastructure: A robust physical infrastructure that enables full-chip analysis using die area tessellation and delivers performance as well as capacity through distributed processing without compromising accuracy of analysis;

-- Support of different design styles at different design stages, i.e. cell-based and custom and different flows such as library (stand alone and in the context of the design), floorplan analysis and detailed routing analysis using either GDSII or DEF formats or using Open Access interfaces;

-- Recognizing memory structures and taking redundancy into account while reporting yield sensitivities for the memories or for full chip is a unique feature that enables designers to trade off area versus yield sensitivity;

-- Fab IP protection: The yield analysis is even more meaningful with actual fab data from the semiconductor manufacturer. The ingenious encryption mechanism developed by Ponte allows the fabs to provide their data to customers without compromising their confidentiality, yet enabling designers to correlate to fab for accurate analysis.

Pricing and Availability

Yield Analyzer is now available for a list price in North America starting at $125,000 per license per year for a single CPU.

About Ponte Solutions

Ponte Solutions, Inc., the design-for-yield company, manufactures and delivers unique, full-chip, model-based software products for semiconductor yield analysis and prediction, enabling designers to perform design-stage yield optimization. Ponte's customers include leading semiconductor manufacturers, foundries and design houses worldwide. Founded in 2002, the company has received funding from US Venture Partners, Incubic LLC, Silicom Ventures LLC and private individuals. The company has offices in Mountain View, California; Grenoble, France; Tokyo, Japan; and Yerevan, Armenia. More information about the company can be found at www.pontesolutions.com.

Ponte Solutions is a trademark of Ponte Solutions, Inc. All other trademarks are properties of their respective owners.

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