ADVISORY/ Sandwork to Demonstrate Silicon Verification and Layout Parasitic Signal Integrity Analysis at DATE; CEO on panel

MOUNTAIN VIEW, Calif., February 28, 2006 -- Sandwork Design Inc. will present its new silicon verification capability and layout parasitic signal integrity analysis for designers of integrated circuits (ICs) and systems on chip (SoC) at the Design Automation and Test in Europe (DATE) conference in Munich, Germany, from March 6-10, 2006.

The new silicon sampled data verification capability gives digital and mixed-signal designers oscilloscope waveform data reading capability and the option to display IBIS models. Layout and parasitic signal integrity analysis capability allows designers to do post-layout simulation cross-probing from an ideal schematic and detailed standard parasitic format (DSPF) netlist visualization results. Sandwork will be in Booth F41 at DATE. In addition, CEO Jack Yao will be on a panel entitled "Competition vs. Partnership: Turning partnerships into improved business results" in the OCP-IP Pavillion between 3:00-4:00pm on Tuesday, March 7.

About Sandwork Design
Sandwork Design, Inc. develops transistor-level debugging and waveform analysis software that provides access to and support for analysis of data from simulation, hardware measurement, and system-level modeling. Quick and easy silicon results analysis of complex analog and mixed-signal semiconductors and systems on a chip (SoCs) allows customers to shorten design cycles and improve chip performance. Headquartered in Mountain View, Calif., Sandwork is privately held and has been profitable since 2001. Further information is available at the company's website at www.sandwork.com.


Contacts:
Sandwork Design
Wu-Yi Chin, 650-988-9934, Email Contact

Cayenne Communication for Sandwork Design
Linda Marchant, 919-451-0776, Email Contact



WaveView Analyzer is a trademark of Sandwork Design, Inc. All other brand and product names appearing in this document are registered trademarks or trademarks of their respective holders.

Rating:


Review Article Be the first to review this article
CST: Webinar

Aldec Simulator Evaluate Now

Featured Video
Jobs
Senior DSP Firmware Engineer for Cirrus Logic, Inc. at Austin, TX
Senior Formal FAE Location OPEN for EDA Careers at San Jose or Anywhere, CA
ASIC Design Engineer for Infinera Corp at Sunnyvale, CA
Design Verification Engineer for intersil at Morrisville, NC
Upcoming Events
Essentials of Electronic Technology: A Crash Course at Columbia MD - Jan 16 - 18, 2018
Essentials of Digital Technology at MD - Feb 13 - 14, 2018
IPC APEX EXPO 2018 at San Diego Convention Center San Diego CA - Feb 24 - 1, 2018
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise