Fujitsu Deploys 65nm Reference Design Flow Based on Cadence Encounter GXL Technology; Fujitsu Extends Consecutive First Silicon Success with 150 ASIC Tapeouts
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Fujitsu Deploys 65nm Reference Design Flow Based on Cadence Encounter GXL Technology; Fujitsu Extends Consecutive First Silicon Success with 150 ASIC Tapeouts

SAN JOSE, Calif.—(BUSINESS WIRE)—Jan. 24, 2006— Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Fujitsu has adopted the Cadence(R) Encounter(R) digital IC design platform, with Encounter RTL Compiler GXL and SoC Encounter(TM) GXL technology, in its new internal reference design flow targeted at 65-nanometer chips. The Encounter-based flow has, to date, produced 150 high-end production ASICs at or below 130 nanometers with all first silicon success, out of which about 30 designs were developed at 90 nanometers.

"At 65-nanometers, there are new design challenges such as yield, process variation and leakage power," said Satoshi Andou, general manager, Design Platform Development Division, Electronic Devices Business Unit of Fujitsu Limited. "We evaluated the Cadence Encounter GXL technologies over the past six months and have been intensively incorporating its new global synthesis and physical implementation technologies into our new reference design flow for 65 nanometers. We appreciate the Cadence team's dedicated contribution to Fujitsu's successful launch of our 65-nanometer technology."

To address design-for-yield (DFY) concerns at 65 nanometers, Fujitsu and Cadence worked together to adopt the Cadence SoC Encounter GXL system's yield-aware physical implementation features. As a result of this joint collaboration, the 65-nanometer reference flow will also include SoC Encounter's Masterplan automatic floorplanner, global physical synthesis (GPS), Encounter NanoRoute(TM) Ultra routing, verification and chip-finishing technology. CeltIC(R) Nanometer Delay Calculator (NDC) and VoltageStorm(R) static analysis are also available to provide signoff-quality SI- and IR-aware timing.

Encounter RTL Compiler logic synthesis is also included in the reference design flow, and Fujitsu has started to evaluate new advanced synthesis features, including automatic physical-layout estimation (PLE) to address 65-nanometer design challenges. Finally, Encounter's RTL-to-GDSII low-power flow enables seamless multi-supply-voltage and multi-threshhold-voltage (Vt) designs, which is featured in the Fujitsu's leading-edge low-power solution using its low-power library.

"As a Premier Design Partner of Fujitsu, we are pleased that our advancements in synthesis, signal-integrity-based timing closure and low-power-design solutions have contributed to Fujitsu's success in a wide variety of markets, including IP and ASIC," said Wei-Jin Dai, corporate vice president, R&D for Cadence. "We applaud Fujitsu's success in maximizing the benefits of the Cadence Encounter platform."

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed-circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

Cadence, the Cadence logo, VoltageStorm, CeltIC and Encounter are registered trademarks. NanoRoute and SoC Encounter are trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Cadence Design Systems, Inc.
Michael Fournell, 408-428-5135

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