EVE has integrated Verific's C++ source code-based parsers, analyzers and elaborators for Verilog, SystemVerilog and VHDL with its ZeBu (for Zero Bugs), a high-performance emulation platform that enables simultaneous hardware and embedded software verification. EVE's fully automated compiler parses RTL code and partitions it for parallel synthesis, dramatically accelerating set-up time prior to emulation.
Dr. Luc Burgun, EVE's chief executive officer and president, remarks: "Verific's HDL Component Software has become the industry standard and for good reason. The software is first rate and the support is outstanding. Verific is an excellent development partner."
"EVE stands out for its continuing innovation and creativity," adds Michiel Ligthart, Verific's chief operating officer. "It sets the pace for verification advances by expanding the technical capabilities of emulation and we're delighted to support its achievements."
About Verific Design Automation
Verific Design Automation was founded in 1999 by electronic design automation (EDA) industry veteran Rob Dekker. It develops and sells C++ source code-based SystemVerilog, Verilog and VHDL front ends -- parsers, analyzers and elaborators -- as well as a generic hierarchical netlist database for EDA applications. Verific's technology has been licensed in many applications, combined shipping more than 45,000 end-user copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: firstname.lastname@example.org. Website: http://www.verific.com.
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Public Relations for Verific Nanette Collins, 617-437-1822 Email Contact