Agere Systems Accelerates Tapeout of High-Performance SOC with Synopsys IC Compiler

IC Compiler Fits Easily in the Agere Flow, Delivers Higher Performance

MOUNTAIN VIEW, Calif., Nov 28 /PRNewswire-FirstCall/ -- Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, today announced that Agere Systems Inc. has used Synopsys' IC Compiler next- generation place-and-route system to tape out a 90-nanometer (nm) multi-core DSP system-on-chip (SoC) for telecom applications. The Agere design team needed to reduce routing congestion on this SoC while meeting timing and power specifications. IC Compiler fit easily into the Agere flow and delivered initial results in just two days. Agere's final results with IC Compiler were completed in less time and showed significantly improved routability and higher performance.

"We were able to easily deploy IC Compiler and produced better results than we could achieve before," said Jill Bennett, engineering director with Agere's Telecommunications Division. "We are encouraged by these excellent results, and are now pursuing IC Compiler deployment across multiple designs."

The new Extended Physical Synthesis (XPS) architecture in IC Compiler -- combined with the tool's multi-threshold capabilities -- enabled Agere to concurrently optimize for timing and power, reducing routing congestion and speeding the time to closure.

"Agere's tapeout success underscores Synopsys' commitment to help customers reduce their time-to-market and deliver chips with higher performance and yield," said Antun Domic, senior vice president and general manager, Synopsys Implementation Group. "We look forward to working closely with customers like Agere to enable their full use of IC Compiler to achieve higher performance and productivity for competitive advantage."

About IC Compiler

IC Compiler is Synopsys' next-generation place-and-route system. It provides superior results and faster time-to-results by extending physical synthesis to full place-and-route, and by enabling signoff-driven design closure. Current generation solutions have a limited horizon because placement, clock tree and routing are separate, disjointed steps. IC Compiler's Extended Physical Synthesis (XPS) technology breaks down these walls by extending physical synthesis to full place-and-route between these steps through a unified, TCL-based architecture that implements innovations in optimization as well as harnessing the best of Synopsys' core technologies in physical synthesis, placement, routing, timing and signal integrity (SI) optimization, power reduction, design-for-test (DFT), and yield optimization.

About Synopsys

Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at www.synopsys.com.

NOTE: Synopsys and the Synopsys logo are registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.

    Editorial Contacts:

    Nancy Renzullo
    Synopsys, Inc.
    (650) 584-1669
    
Email Contact

    Angela Costa
    Edelman Public Relations
    (650) 429-2765
    
Email Contact

CONTACT: Nancy Renzullo of Synopsys, Inc., +1-650-584-1669, or
Email Contact; or Angela Costa of Edelman Public Relations,
+1-650-429-2765, or Email Contact, for Synopsys, Inc.

Web site: http://www.synopsys.com/


Rating:


Review Article Be the first to review this article
CST: Webinar November 9, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Teklatech: Work smart, Not hard
More Editorial  
Jobs
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Upcoming Events
ARM TechCon 2017 at Santa Clara Convention Center Santa Clara CA - Oct 24 - 26, 2017
MIPI DevCon Bangalore 2017 at The Leela Palace Bengaluru India - Oct 27, 2017
The 2017 International Test Conference at Fort Worth Convention Center Fort Worth TX - Oct 31 - 2, 2017
MIPI DevCon Hsinchu City 2017 at Sheraton Hsinchu Hotel Taiwan - Oct 31, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise