Tower Semiconductor Collaborates with Cadence to Deliver Optimized Reference Flow for Specialty Technology Processes; Design Chain Collaboration Accelerates SanDisk's Time-to-Market

MIGDAL HAEMEK, Israel—(BUSINESS WIRE)—Nov. 14, 2005— Tower Semiconductor Ltd. (Nasdaq: TSEM)(TASE: TSEM) today announced a collaboration with Cadence Design Systems, Inc. (NASDAQ:CDNS) to deliver a reference flow targeting system-on-chip (SoC) designs at 0.18-micron using Tower's CMOS mixed-signal process. In addition, Tower has joined the Cadence foundry partner program to enhance the combined offering of solutions to the customer.

The reference flow utilizes the Cadence(R) Encounter(R) digital IC design platform, the Virtuoso(R) custom IC design platform and the Incisive(R) functional verification platform, and libraries from Tower and third-party providers. This RTL-to-GDSII reference flow optimizes the design chain by enabling a low-risk, predictable path from design to volume production. The flow reduces iterations in the design phase and improves accuracy through model optimization.

"We were impressed by the way that Cadence's Virtual Computer Aided Design (VCAD) Services built a reference flow and implemented it within Tower's technology, ensuring consistency throughout all design steps and enabling the full potential of Tower's 0.18-micron process and Cadence's software," said Geoff Gongwer, senior director, ASIC and CAD at SanDisk Corporation (Nasdaq:SNDK). "Using the reference flow on a critical design enabled us to avoid unforeseen physical design issues and to achieve silicon success at Tower."

"The increased mixed-signal content in today's SoCs requires access to detailed and accurate process information during the design phase," said Jan Willis, senior vice president, Industry Alliances, at Cadence. "Collaboration through the design chain produces the process design kits and libraries that provide designers with this information for implementing their design. This jointly-developed reference flow with Tower provides a fully validated methodology that will improve the productivity of customers designing with Cadence software targeting the Tower 0.18-micron process."

"The development of this reference flow is another step in the ongoing collaboration between Tower and Cadence," said Yaakov Milstain, vice president and general manager of design services at Tower Semiconductor Ltd. "The reference flow, based on Cadence design platforms, enables our customers to realize a much faster path to production silicon using Tower's leading-edge specialty process technologies."

Tower has qualified Cadence as part of the Tower Authorized Design Center (TADC) program to expand customer access to Cadence's leading design services capabilities.


The Reference Flow is available through Tower. Contact either your Tower or Cadence account manager for more information.

Additional details about the Candence foundry partner program can be found at

About Tower Semiconductor Ltd.

Tower Semiconductor Ltd. is a pure-play independent specialty foundry established in 1993. The company manufactures integrated circuits with geometries ranging from 1.0 to 0.13 micron; it also provides complementary technical services and design support. In addition to digital CMOS process technology, Tower offers advanced non-volatile memory solutions, mixed-signal, RF-CMOS and CMOS image-sensor technologies. To provide world-class customer service, the company maintains two manufacturing facilities: Fab 1 has process technologies from 1.0 to 0.35-micron and can produce up to 16,000 150mm wafers per month. Fab 2 features 0.18-micron and below standard and specialized process technologies, and has the current capacity of up to 15,000 200mm wafers per month. Tower's Web site is located at

Safe Harbor

This press release includes forward-looking statements, which are subject to risks and uncertainties. Actual results may vary from those projected or implied by such forward-looking statements. Potential risks and uncertainties include, without limitation, risks and uncertainties associated with market demand for 0.18-micron technology manufacturing services. A more complete discussion of risks and uncertainties that may affect the accuracy of forward-looking statements included in this press release or which may otherwise affect our business is included under the heading "Risk Factors" in our most recent Annual Report on Form 20-F and in our Form F-3, as amended, as were filed with the Securities and Exchange Commission and the Israel Securities Authority.

Tower Semiconductor USA
Michael Axelrod, 408-330-6871

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