"Some of these interfaces have been difficult to test for our customers, there isn't boundary-scan available on these pins and pogo-pin tests are not an option at high speed. Due to the speeds of the connections they are susceptible to the affects of noise, cross-talk, poor grounding, jitter and imperfections in the interconnect between the ICs" said CJ Clark, Intellitech CEO and past IEEE 1149.1/JTAG working group chairperson. "These can be difficult to find and isolate without having a solid test strategy in place such as this." "There has been some confusion in the marketplace due to past announcements from vendors testing "high-speed SERDES" with IEEE 1149.6 the standard for testing AC coupled interconnects. IEEE 1149.6 is a wonderful standard, however it is still testing for stuck-at faults, misplaced or mis-valued capacitors; it doesn't test the connections at-speed at all", Clark continued. "We have an early adopter that we are working with now as we finalize the feature sets of the tests. The BERT IP and DDR IP will be available for purchase after the first of the year" Clark added.
Intellitech's TEST-IP(TM) family provides patented infrastructure IP that enables customers to lower the cost of designing, debugging, producing and maintaining electronic systems. Intellitech's proprietary solutions enable customers to build self-testable and in-the-field re-configurable products with the least amount of engineering resources and at the lowest cost. Intellitech lowers production costs by embedding test or enabling concurrent test of electronic assemblies during production test and burn-in. The unified test and configuration approach enables customers to lower manufacturing test costs, provide field adaptable products and retard product obsolescence with field upgrade-able logic.
Intellitech Kareen Lefoley, 603-868-7116x106 Fax. 603-868-7119 Email Contact