Cadence Supports STARC Technology to Improve Delay Test Quality; Top Japanese Research Center's Quality Model Validates Superior Coverage of Cadence Encounter True-Time Delay Test

SAN JOSE, Calif.—(BUSINESS WIRE)—Nov. 7, 2005— Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a cooperative quality modeling initiative with the Semiconductor Technology Academic Research Center (STARC). The two companies are working together to estimate the semiconductor device outgoing quality level as a function of delay test robustness applied in manufacturing. The first result of the initiative is STARC's quality model's validation of Cadence(R) Encounter(R) True-Time Delay Test.

Delay defects slow signal transitions in nanometer-scale designs, making delay testing critically important. Without the use of a truly effective delay test, delay defects go undetected and possibly cause failures later in the supply chain, causing significant issues in customer satisfaction and higher warranty costs. Assessing the effectiveness of delay testing by examination of test coverage percentage can be misleading because the actual timing of the test for each fault determines if a delay defect of a given size is detected or not. To address this, Cadence supplies the market with Encounter True-Time Delay Test, the industry's first automatic test pattern generator (ATPG) that can automatically generate timing accurate delay tests.

"Studies of our member companies have shown that traditional delay test tools do not detect an increasing number of critical small delay defects," said Yasuo Sato, senior manager, Test Methodology Group at STARC. "STARC has developed a statistical delay quality model (SDQM) methodology to quantify the effectiveness of a given delay test method. Cadence has successfully implemented support and validated results for this technology. Based on the results observed with our experiments, we expect that Encounter True-Time Delay Test can be very effective in detecting small delay defects, and thus improve the chip's outgoing quality level."

In order to better quantify the differentiated value of Encounter True-Time Delay Test, Cadence and STARC worked together to validate an SDQM that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides an educated estimate of the quality level of the chip as a function of defects that cause delay-related failures and as a function of the timing of the test for each fault.

"Our cooperation with STARC demonstrates the advantages True-Time Delay Test provides customers," said Sanjiv Taneja, general manager of Encounter Test at Cadence. "Be it in terms of detecting test escapes that later fail at system test or estimating outgoing quality levels, we are confident that True-Time Delay Test will bring significant and differentiated benefit for nanometer designs."

Part of the Cadence Encounter digital IC design platform, Encounter True-Time Delay Test is also fully compatible with Encounter Diagnostics, the industry's leading-edge yield diagnostics product. In the effort to accelerate yield ramp, customers will benefit from the additional test efficiency of True-Time Delay Test and the subtle defects detected by it can be driven to root cause by Encounter Diagnostics.

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, printed circuit boards and systems used in consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 5,000 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, the Cadence logo, and Encounter are registered trademarks of Cadence Design Systems in the United States and other countries. All other trademarks are the property of their respective owners.



Contact:
Cadence Design Systems, Inc.
Judy Erkanat, 408-894-2302

Email Contact



Review Article Be the first to review this article
Downstream : Solutuions for Post processing PCB Designs


Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Jobs
Technical Support Engineer for EDA Careers at Freemont, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
CAD/CAM Regional Account Manager (Pacific Northwest) for Vero Software Inc. at Seattle, WA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017
Verific: SystemVerilog & VHDL Parsers
DAC2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy