Advanced Testbench Techniques Critical for Multi-Protocol Verification Environment at Chip and System Levels
"Our advanced field programmable gate array (FPGA) designs require sophisticated verification tools and techniques to help ensure optimum performance for our customers," said Kostas Kalaitzidis, lead FPGA verification engineer at Cedar Point. "Synopsys' VCS NTB technology allowed us to easily write testbench drivers and monitors for a wide variety of complex packet-based protocols and to develop directed and randomized tests that reflect cable operators' field needs."
VCS NTB technology with support for the SystemVerilog and OpenVera(R) languages deploys a unique, single-compiler architecture to simultaneously optimize design, testbench, assertions and coverage, delivering up to five times faster verification performance compared to independent testbench and simulation environments. VCS NTB supports advanced testbench capabilities such as constrained-random stimulus generation, object-oriented programming, advanced data types and more. The VCS solution's built-in code and functional coverage engines help ensure more predictable verification closure by enabling engineers to accurately monitor verification progress over time, and to determine when verification is complete.
"Synopsys' VCS NTB technology is unique in the industry," said Farhad Hayat, vice president of Marketing, Verification Group, Synopsys, Inc. "It brings advanced verification methods, including coverage, assertions and testbench automation, directly into the simulator to yield a fast, comprehensive verification solution. Our customers are routinely seeing speedups of up to five times when they use VCS NTB."
Synopsys Discovery Verification Platform
The Discovery Verification Platform is a unified environment that provides high performance and efficiency of interaction among all platform components, including mixed-HDL simulation, mixed-signal, system-level verification, assertions, DesignWare(R) verification intellectual property, code coverage, functional coverage, testbenches and formal analysis. Combined with support for industry-standard hardware design and verification languages, including Verilog, VHDL, SystemVerilog, SystemC(TM) and OpenVera, and Synopsys' proven Reference Verification Methodology, the Discovery Verification Platform helps designers achieve higher levels of verification productivity by contributing to first-time silicon success within required project cycles.
Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.
NOTE: DesignWare, OpenVera and VCS are registered trademarks of Synopsys, Inc. Discovery is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Editorial Contacts: Isela Warner Synopsys, Inc. 650-584-1644 Email Contact Suraya Akbarzad Edelman 650-968-4033 Email Contact
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