PARIS, France, and TOKYO, Japan, October 20th, 2005 - Avertec, specialist in the back-end verification of complex designs announced that it has partnered with Jedat Inc. (Japan EDA Technologies Inc.), a leading EDA systems provider in Japan.
"We are quite pleased to be associated with Avertec and its design solution which was adopted by a leading Japanese semiconductor company that we recently engaged" said Taguchi Yasuhiro, EDA Sales Division Manager, Jedat.
"This is a major boost in Avertec's expansion" added Manuel de Almeida, Sales Manager, Avertec. "By partnering with Jedat and providing local support for our HiTas and Yagle proven solutions, Avertec is committed to ensure a long-term success of its Japanese customers."
Jedat Inc. (JEDAT), formerly the EDA Systems Division of Seiko Instruments Inc. (SII) started its business on February 2, 2004 as a new and independent company. SII launched its EDA systems business in 1980, deploying Japanese-technologies to become one of the leaders in the EDA field. Located in Tokyo, Japan, JEDAT took over SII's well-known SX Series product line and continues its focus on the fields of full-custom design, DFM, and mask verification. For more information visit:
Avertec is a privately held company created in 1998 and headquartered in the Paris area, France.
Avertec's HiTas platform provides advanced transistor-level static timing and signal integrity analysis. It has been developed to provide engineers with complete timing and SI coverage on their digital custom designs, as well as IP-reuse through timing characterization. The advanced timing engine provides high-speed analysis with Spice accuracy for 90nm and beyond.
The company has a sales office in San Jose, California and represented by distributors in Japan and in Asia. Avertec is a member of the EDA Consortium.
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