The latest Allegro technology shortens design cycle time by enabling team-based PCB system design throughout the design flow. The entire breadth of the Allegro product line has been enhanced with greater productivity and ease-of-use capabilities. It further strengthens the design chain by helping IC companies distribute Spectre(R) transistor-level models so that their customers can design-in complex ICs faster. The release includes new technology for multi-style design creation, real-time design for assembly (DFA) driven placement and an improved constraint-driven design flow.
"We are especially pleased with Allegro's new real-time DFA driven placement capability," said Charlie Davies, ECAE Application Engineer of Harris Government Communication Systems Division. "This feature guides component placement, allowing us to create manufacturable designs appreciably faster. This capability further enhances Cadence's Constraint Driven PCB Design Flow."
Allegro now includes Allegro Design Editor, the industry's first PCB multi-style design creation environment. Allegro Design Editor helps make design creation up to 10 times faster with a spreadsheet-like interface, schematics and Verilog-language-sensitive editor customized for PCB design. This new design creation paradigm for capturing PCB and multi-component package designs provides a connectivity-based solution introducing an easy-to-learn, easy-to-use environment that supports multiple styles for creating design intent.
"With a new design entry paradigm leveraging a core constraint management system all the way to the back end of the design process, the latest advances in the Cadence Allegro platform provide us with a design flow tailored to our needs," said Tim Kent, vice president of engineering at high performance computing system vendor Liquid Computing. "Some of our designs are highly constrained with large pin-count devices. With Allegro Design Editor, we believe Cadence is uniquely positioned to help customers like us dramatically accelerate design creation for these complex PCB designs. We also plan to adopt the new Allegro design partitioning technology in the near future."
"This latest enhancement to our SPB product line means our customers have a real-time approach to design for assembly and the technology advancements they need to address their most pressing challenges in the constraint-driven PCB design flow," said Charlie Giorgetti, corporate vice president and general manager of system design at Cadence. "This latest release of Allegro is another example of how Cadence continues to lead the way in the silicon-package-board co-design market."
Available now, the latest Allegro release accelerates design creation time by improving design reuse with schematics on front-end constraints stored with each schematic block. Real-time DFA Design Rule Checker (DRC) guides the placement of components for faster design. A component revision manager in design entry HDL automatically verifies that schematic symbols are up to date to prevent the use of outdated parts previously not discovered until later in the design cycle.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 4,700 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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Cadence Design Systems Judy Erkanat, 408-894-2302 Email Contact