UltraScan further reduces test application time and test pin-count for high-speed I/O pads
SUNNYVALE, California, July 19, 2005 - Design-for-Test (DFT) leader SynTest Technologies today announced that it would be offering a software product called UltraScan�. UltraScan with its Time-Division De-Multiplexing (TDDM) and Multiplexing (TDM) circuits is able to utilize the unutilized bandwidth available on high-speed channels on the ATE during low speed scan-shift operation, and thereby offer overall shorter test load times and also provide better transition fault coverage for high-speed I/O pads on the device. Further, due to the pin reduction realized with TDDM/TDM, a small number of high-speed I/O pads are adequate to run a scan-ATPG test for a design with a large number of internal scan-chains of shorter length.
UltraScan is used with SynTest's VirtualScan to further reduce test application time. SynTest's VirtualScan itself offers a significant reduction in the cost of semiconductor testing by reducing test data volume and test cycle volume by 5x - 50X, thereby reducing the necessity of expensive memory space on Automatic Test Equipment (ATE). An evaluation on a 4.2-million gate circuit showed a reduction in test time of 18.7X through VirtualScan and an additional reduction of 10X through UltraScan, giving a total reduction in test time of 187X.
Implementing UltraScan on a 4.5-million gate circuit with 32 internal scan-chains, using a de-multiplexing ratio of 8, it was possible to scan-test the device on a lower cost ATE limited to only 4 test channels. This demonstrated that it was possible to reduce the number of external scan input/output ports to 4, resulting in test pin-count reduction as desired, and without increasing the test application time.
"Testing for stuck-at faults and Iddq is adequate to ensure acceptable quality levels for ASICs designed for geometries larger than 130 nm. However, for ASICs designed for 130 nm or smaller (nanometer) geometries, many defects are no longer static. They become delay defects and it becomes necessary to use delay tests to detect the transition faults and path delay faults. Since these delay tests are more complicated than tests for stuck-at faults, many more test patterns are required resulting in more time on ATE and more memory to store patterns. End result greater is test cost. It is in this environment that UltraScan together with VirtualScan, help in reducing the cost of ASIC testing", commented Dr. Ravi Apte, SynTest's Sr. VP for Business Development.
"We, with our proprietary technologies, have been at the forefront of the fight to not let pattern volume cause test costs to get out of hand. Hence, in spite of the ever increasing complexity and size of SOC designs, our customers have been kept relatively immune to the exploding test costs," remarked Dr. L.-T. Wang, President and CEO of SynTest Technologies.
About Scan and Semiconductor Test
ASIC semiconductor testing cost has been increasing steadily over the past few years and is now a major part of the overall manufacturing cost of chips. With the average ASIC design size expected to grow to greater than 5 million gates in the near future, new approaches such as SynTest's UltraScan and VirtualScan are needed to reduce test application time and test data volume.
The UltraScan architecture consists of three major parts:
- A Time-Division De-Multiplexing (TDDM) circuit placed between high-speed I/O pads for driving scan chains and the internal VirtualScan broadcaster input ports
- A Time Division Multiplexing (TDM) circuit placed between the internal VirtualScan compactor output ports and high-speed I/O pads to bring out scan chains
- VirtualScan broadcaster and compactor circuits As the TDDM and TDM circuits are generated as RTL blocks it eases the overall design floor planning decisions carried out at the RTL stage. The area impact of the TDDM and TDM is predictable and extremely small.
A paper detailing the UltraScan architecture, titled "UltraScan: Using Time-Division Demultiplexing/Multiplexing (TDDM/TDM) with VirtualScan for Test Cost Reduction", will be presented at the International Test Conference (ITC) 2005 in Austin, TX, November 2005.
SynTest Technologies, Inc. develops and markets advanced DFT and Design-for-Debug/Diagnosis (DFD) tools, throughout the world to semiconductor companies, ASIC designers and test groups. Headquartered in Sunnyvale, California, the company has offices in Taiwan, Korea and Japan. The Company's products improve an electronic design's testability and fault coverage and result in reduced defect levels, reduced costly tester time, and reduced slippage in time-to-market. These products include tools for Built-in Self-Test (BIST) for logic and memory, boundary-scan synthesis, DFT testability analysis, scan synthesis, ATPG, concurrent fault simulation, silicon debug and diagnosis. More information is available at www.syntest.com.
SynTest Technologies Inc. is headquartered at 505 South Pastoria Ave., Suite 101, Sunnyvale, California 94086, Phone: 408-720-9956, E-Mail: Email Contact
Press Contact: Nayan Pradhan, 408-720-9956 ext. 301, Email Contact
ATE: Automatic Test Equipment
ATPG: Automatic Test Program Generation
BIST: Built-In Self Test
BSD: Boundary Scan Design
DFD: Design for Debug/Diagnosis
DFT: Design For Test
TurboBIST-Memory, TurboBSD, TurboCheck-Gate, TurboDFT, TurboFault, TurboScan, UltraScan and VirtualScan are trademarks of SynTest Technologies. All other company or product names are the registered trademarks or trademarks of their respective owners.