Credence and Cadence Collaboration Validates Flow for Faster Yield Diagnostics

Faster Time-to-Volume Is a Result of Work by Credence and Cadence Enabling Higher Product Quality, Faster Test Throughput and Rapid Defect Resolution for Today's Most Yield-Challenging Nanometer Designs

MILPITAS, Calif., July 18 /PRNewswire-FirstCall/ -- Credence Systems Corporation (NASDAQ: CMOS) a leading provider of test solutions from design to production for the worldwide semiconductor industry, today announced it has validated a yield improvement flow between their Sapphire test platform and Cadence Encounter(TM) Test. Sapphire supports Cadence Encounter Test True-Time Delay Test patterns, which are STIL based, as well as Cadence Encounter Diagnostics input format for capturing test failures from Sapphire. This validated flow reduces test escapes and improves the speed for defect resolution in designs using 90 nm or less.

Delay testing is critical for nanometer-scale designs as defects cause slow transitions. At-speed delay testing is intended to detect these problems, but as many as 50 percent of these defects can escape detection because they are tested on non-critical paths. Also, traditional at-speed fixed-time ATPG does not constrain the test patterns to the capabilities of the tester, so in many cases, test patterns violate tester pin timing and have to be discarded. The combination of these two limitations results in substantially lower product quality and slower time to manufacturing test.

Maximizing Yield with the Sapphire Test Platform

Since its introduction, Sapphire delivers the performance necessary to maximize device yields. From world-leading timing accuracy to delivering the first scalable system to 3.2 Gbps, Sapphire's performance and throughput set the industry standard to beat for cost of test. As the industry moves beyond 90 nm, yields will be impacted by new process defects such as delay faults.

"Delay defects are a dominant cause of yield loss in designs at 90 nm," said Dave Ranhoff, President and CEO at Credence. "A Sapphire used in conjunction with Cadence Encounter True-Time Delay Test as well as Cadence Encounter Diagnostics provides semiconductor companies an optimized engineering and production test development path for detecting and diagnosing these most difficult problems. Supporting the design for yield methodologies developed by the major EDA suppliers like Cadence is important to our customers and fits into our broader vision of how Credence participates in design debug all the way to production test."

Improved Delay Tests and Rapid Diagnostics Improve Time-to-Yield

Cadence Encounter True-Time Delay Test is the industry's first delay test ATPG that uses actual post layout design timing information and the specification of the tester's timing capabilities to automatically generate faster-than-at-speed delay tests in a single pass. In addition, the companies are announcing validation of the path for rapid resolution of yield loss using the Sapphire and Cadence Encounter Diagnostics.

"At 90 nm the major issue facing manufacturers is to quickly resolve subtle design-process interactions that are not predictable before actual silicon and that are difficult to isolate within silicon," stated Sanjiv Taneja, Group Director at Cadence Design Systems Inc. "Traditional ATPG-based diagnostics tools are typically less than 40 percent accurate at 130 nanometers and do not support volume operation, dynamic diagnostics, customizable fault modeling, or vectors generated by other ATPG tools."

Validating the Defect Diagnostics Flow

Cadence Encounter Diagnostics was developed specifically to accelerate nanometer yield in high-volume manufacturing environments. In volume mode, the tool identifies the most critical design-related issues based on analyzing a statistically significant sample size. In precision mode, it precisely locates the root cause defects, which can then be verified in a physical failure analysis lab. Each of these modes requires a compatibility with the ATE to assure that ATE fail data whether for a single device or thousands of failures across multiple wafer lots can pass to Cadence Encounter Diagnostics. Credence's Sapphire failure logs are compatible with Cadence Encounter Diagnostics' Chip Pad Pattern (CPP) format.

About Credence

Credence Systems Corporation is the industry's leading provider of design-to-test solutions for the global semiconductor industry. With a commitment to applying innovative technology to lower the cost-of-test, Credence delivers competitive cost and performance advantages to integrated device manufacturers (IDMs), wafer foundries, outsource assembly and test (OSAT) suppliers and fabless chip companies worldwide. A global, ISO 9001-certified company with a presence in 20 countries, Credence is headquartered in Milpitas, California. More information is available at .

NOTE: Credence is a registered trademark, and Credence Systems and Sapphire are trademarks of Credence Systems Corporation. Other trademarks that may be mentioned in this release are the intellectual property of their respective owners.

     Company Contact:
     Judy Dale
     Vice President, Marketing Communications
     Credence Systems Corporation
     Phone: 408-635-4309
     FAX: 408-635-4986
Email Contact

CONTACT: Judy Dale, Vice President, Marketing Communications of Credence
Systems Corporation, +1-408-635-4309, or fax, +1-408-635-4986, or
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