Nethra Speeds Tapeout of Image Processor with Cadence Encounter RTL Compiler; Cadence Global Synthesis Technology Enables Fast Timing Closure While Reducing Die Size and Power Consumption

ANAHEIM, Calif.—(BUSINESS WIRE)—June 14, 2005— Cadence Design Systems, Inc. (NYSE: CDN) (Nasdaq: CDN) today announced that Nethra Imaging successfully taped out its first product, the NI-2050 image processor designed for mobile handset applications, using Cadence(R) Encounter(TM) RTL Compiler synthesis.

The use of Encounter RTL Compiler helped Nethra achieve a very short design cycle with no room for error, first-time working silicon, the smallest possible die size, low cost, and the least possible power dissipation. ASIC designers achieved these goals in record time because Encounter RTL Compiler provided an efficient and accurate netlist for timing closure.

"Encounter RTL Compiler was an integral part of our design flow," said Ravi Bhatnagar, senior vice president of Engineering at Nethra. "Our engineers have found the tool to be fast and powerful. The synthesis results were up to our expectation, and it helped us save power and area. RTL Compiler, along with other tools in the flow, helped us achieve first-time working silicon."

Encounter RTL Compiler's global synthesis approach enables simultaneous optimization of timing, power, and area in a top-down run. This produces a netlist that goes through place and route more cleanly with better results.

"We were able to incorporate Encounter RTL Compiler into our flow very quickly," said Deepak Tripathi, Nethra's ASIC design manager. "It was able to quickly and easily synthesize our design top down with multiple clock domains. RTL Compiler also has a very impressive set of features to support low-power design and design-for-test techniques. The quality of the netlist was such that we were able to close timing with place and route in record time. We received excellent support both during initial adoption and while customizing the synthesis flow to best suit our needs. RTL Compiler's flexibility and capabilities are very impressive."

Interconnect related parameters in nanometer designs require a new metric for synthesis results that includes performance, area, and power measured with wires. Cadence defines this as Quality of Silicon (QoS). Cadence Encounter RTL Compiler's global synthesis enables designers to achieve the highest QoS in less time and with less effort.

"We are excited that Encounter RTL Compiler played a significant role in enabling Nethra Imaging to meet its design goals and successfully sample its first product," said Dr. Chi-Ping Hsu, corporate vice president at Cadence. "This is another proof point of how Encounter RTL Compiler enables customers to implement smaller, faster, and cooler chips in less time."

During the last 12 months, 75 new customers adopted Encounter RTL Compiler.

About Nethra

Nethra Imaging is a privately-held semiconductor company focused on delivering imaging solutions for a wide range of digital consumer applications. The company's product roadmap uses proprietary algorithms to build flexible, fully programmable digital camera chips for mobile handsets. The core technology can address the needs of other imaging markets in the future. Incorporated in 2003, Nethra is located in Cupertino, Calif. and began full operations in January 2004. The company's leaders are a team of established entrepreneurs with a wealth of experience in imaging and silicon development. Nethra is fully-funded and entering the market in 2005 with a family of image processors for the rapidly growing mobile handset camera market. For more information, visit

About Cadence

Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2004 revenues of approximately $1.2 billion, and has approximately 4,700 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at

Cadence and the Cadence logo are registered trademarks, and Encounter is a trademark of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

Cadence Design Systems, Inc.
Michael Fournell, 408-428-5135

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