Virage Logic Accelerates Silicon Success with Integrated Partner Solutions at 2005 Design Automation Conference

VIP Partner Pavilion, Tutorials, Presentations and DFM Lunch Panel Highlight Breadth of Integrated Partner Solutions

FREMONT, Calif., June 7 /PRNewswire-FirstCall/ -- Virage Logic Corporation (NASDAQ: VIRL), a pioneer in Silicon Aware IP(TM) and leading provider of semiconductor intellectual property (IP) platforms, will demonstrate how to accelerate silicon success with integrated partner solutions at the 42nd Design Automation Conference (DAC) June 13 - 16, 2005 which is being held at the Anaheim Convention Center in Anaheim, California. With the support of 15 VIP Partners including leading Design Services companies, Electronic Automation Design (EDA) and Test solutions suppliers, Foundry partners and IP providers, Virage Logic will showcase complementary, integrated solutions in a special VIP Partner Pavilion (booth #406).

The extensive partner activities complement Virage Logic's main booth (#412), DAC Management Day programs and Hands-on Tutorial sessions that will demonstrate the company's leadership at advanced process nodes, which results in high-yielding, highly reliable semiconductor IP, from 130nm to 65nm. (See related release "Virage Logic's DAC Program Outlines How to Proceed with Confidence in the Nanometer Era of 130nm and Below.")

Visitors to Virage Logic's VIP Partner Pavilion will learn how Virage Logic and its partners team to provide mutual customers with high quality, silicon-proven, integrated solutions that address design requirements, deliver optimum manufacturability and maximum yield for complex System-on-Chip (SoC) designs. VIP Partner Pavilion participants include: Premier sponsors MIPS Technologies and TSMC, Gold level sponsors Cadence, Chartered, PDF Solutions and Synopsys, Silver level sponsors Alchip, Apache, Magma, Sequence, Silterra and Tensilica, and Bronze level sponsors EL & Associates, Tower, and UMC.

In addition to the demos and presentations in the VIP Partner Pavilion, a VIP lounge martini bar and raffle drawing will be co-hosted with the Premier sponsors on Monday, June 13, from 5 p.m.- 6 p.m. during the DAC Happy Hour.

As part of the DAC tutorial program, Virage Logic is co-hosting the following hands-on tutorials with several of its VIP Partners:

    --  "Designing Extendable Cores with Low-Cost Metal Programmable
        Technology" on Tuesday, June 14, from 2 p.m. - 5 p.m. in Room 211AB.
        This hands-on tutorial session with CoWare(R) Inc., Magma(R) Design
        Automation Inc., MIPS Technologies, Inc., is part of the Design for
        Manufacturing track. Attendees will observe a complete system-level
        design process, starting from exploring the system architecture and
        trading-off hardware and system software partitioning. Registration
        cost is $75.00 per person with limited seating.
    --  "Using Configurable Processors to Replace RTL Blocks" on Wednesday,
        June 15, from 2 p.m. - 5 p.m. (Room TBA) Tensilica, Inc. and Virage
        Logic will co-host this hands-on tutorial session as part of the
        System-Level Design and Verification Track, demonstrating how to
        design a configurable processor with equivalent performance to
        hand-coded RTL using Tensilica's XPRES compiler, which automatically
        analyzes C code to determine the best processor configuration and
        extensions. The tutorial shows how to evaluate and select the optimal
        embedded memory IP for Tensilica's Xtensa processor configurations
        using a web-based portal interface from Virage Logic. Participants can
        also expect to learn the performance impact of various memory
        configurations, and how important it is to tightly match the memory to
        the processor configuration. Registration cost is $75.00 per person
        with limited seating.

Virage Logic is an invited speaker in the following VIP Partner events and booths:

    --  Synopsys Interoperability breakfast, Wake Up to Wireless! Enabling
        Complex Designs with Advanced Libraries and IP, at the Marriot Anaheim
        Hotel, Ballroom Marquis North, on Wednesday, June 15 from 7:30 a.m. to
        10 a.m. Virage Logic is showcasing their ASAP Logic(TM) Metal
        Programmable and Standard Cell Libraries at the breakfast.
    --  Magma's booth (#2250), highlights Virage Logic presenting on Monday,
        June 13, at 4 p.m.; on Tuesday, June 14, at 5 p.m.; and Wednesday,
        June 15, at 12 p.m. Virage Logic is presenting its integrated Silicon
        Aware IP for enabling optimum yield, higher performance, superior
        quality and greater reliability at advanced technology nodes.
    --  UMC's booth (#1801), features Virage Logic on Monday, June 13 at
        1:45 p.m. and on Tuesday, June 14 at 2:45 p.m. The presentation
        demonstrates how Virage Logic partners with UMC to provide IP that is
        optimized for yield, manufacturability and reliability as well as how
        Silicon Aware IP solutions benefit UMC and Virage Logic's mutual

Finally, Virage Logic is teaming with TSMC to co-host a thought-provoking lunch panel session: DFM -- The Path to Profitability. The roundtable session, hosted by Bryan Lewis from Garter, will explore the DFM challenges faced at advanced process nodes and debate such issues as products versus services, front- or back-end investing for DFM, and choosing the right sacrifices or trade-offs from the perspectives of both the suppliers and users. The panelists will include: Magdy Abadir, Freescale; Dr. Edmund Cheng, Synopsys; Bob Dunnigan, Sigmatel; Anoop Khurana, Ikanos; Kuo Wu, TSMC; and Dr. Yervant Zorian, Virage Logic. The luncheon will be held on Wednesday June 15, at the Anaheim Convention Center, Room 202B from 11:30 a.m. to 1 p.m. To register, visit

For more information about 2005 DAC, or to register for a tutorial session, please visit .

About Virage Logic's VIP Partner Program

The Virage Logic VIP Partner Program brings together technology and business alliances with partner companies to provide a broad range of complementary solutions for SoC design including Design Services, EDA/Test, Foundry, and Intellectual Property (IP). The VIP Partner Program's mission is to help increase interoperability and provide access to complete solutions that enable mutual customers to accelerate silicon success by reducing design time and improving manufacturability. For a complete listing of Virage Logic's VIP Partners, visit

About Virage Logic

Founded in 1996, Virage Logic Corporation rapidly established itself as a technology and market leader in providing advanced embedded memory intellectual property (IP) for the design of complex integrated circuits. Today the company is a global leader in semiconductor IP platforms comprising embedded memories, standard cells, and I/Os and is pioneering the development of a new class of IP called Silicon Aware IP. Silicon Aware IP tightly integrates Physical IP (memory, logic and I/Os) with the embedded test, diagnostic, and repair capabilities of Infrastructure IP to help ensure manufacturability and optimized yield at the advanced process nodes. Virage Logic's highly differentiated product portfolio provides higher performance, lower power, higher density and optimal yield to foundries, integrated device manufacturers (IDMs) and fabless customers who develop products for the consumer, communications and networking, hand-held and portable, and computer and graphics markets. The company's comprehensive quality efforts are validated in its FirstPass-Silicon Characterization Lab, which helps ensure high quality, reliable IP across a wide range of foundries and process technologies. Headquartered in Fremont, California, Virage Logic has R&D, sales and support offices worldwide. For more information, visit


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