Program Showcases Silicon Aware IP for Dramatic Yield Improvement
Virage Logic's extensive DAC program will help attendees learn how the company's Silicon Aware IP and entire portfolio of IP products address the complex design and manufacturing challenges presented at 130nm and below. Virage Logic's booth (#412) will feature IP experts showcasing the company's Platforms, Memories and Silicon Aware IP product presentations while the private suites will provide more detailed overviews of the company's entire product portfolio, including product roadmaps under non-disclosure agreement (NDA). To take advantage of online registration and book a meeting with Virage Logic at DAC, visit http://www.viragelogic.com/render/content.asp?id=510 .
Dr. Yervant Zorian, vice president and chief scientist at Virage Logic has organized the following sessions for DAC's Management Day being held on Tuesday, June 14:
-- Session 100, "Choosing Flows and Methodology for SoC Design," 2 p.m. to 4 p.m. in Room 207D. This session will highlight how the business performance, design and manufacturing flows and methodologies of SoC companies are being impacted by the move to new semiconductor technology. Speakers from Freescale Semiconductor and PMC-Sierra will provide an overview of changing needs and corresponding management decision criteria aimed at ensuring the right design choices.
-- Session 150, "How to Determine the Necessity for Emerging Solutions" 4:30 p.m. to 6:30 p.m. in Room 207D. This session will show how applications for today's chips require different types of optimizations, necessitating the adoption of emerging products and solutions to meet the new requirements. Speakers from Cisco Systems, eSilicon Corporation, Philips Semiconductor and Intel will discuss today's emerging solutions and their economic impact.
Virage Logic will also host its second annual analyst briefing to update the financial community on the company's Silicon Aware IP solutions for maximizing yields, increasing reliability and speeding time-to-volume at 130nm and below. This invitation-only briefing is being held at the Anaheim Convention Center, Room 303C, on Monday, June 13 from 9:30 a.m. to 11:00 a.m. For further information, please email Email Contact.
Virage Logic is also showcasing an extensive program with its partners including a Virage Logic VIP Partner Pavilion in booth #406, presentations in a number of partner company booths, co-hosting two DAC tutorials and co-sponsoring a Design for Manufacturing luncheon with TSMC. (Please see related release "Virage Logic Accelerates Silicon Success with Integrated Partner Solutions at 2005 Design Automation Conference").
For more information about 2005 DAC, or to register for a tutorial session, please visit http://www.dac.com/42nd/index.html .
About Silicon Aware IP
Silicon Aware IP tightly integrates Physical IP (memory, logic and I/Os) with the embedded test, diagnostic, and repair capabilities of Infrastructure IP. The result is high-yielding, highly reliable semiconductor IP at 130-, 90- and now 65nm. Silicon Aware IP is essential at advanced process nodes, where yield problems can prohibit early adoption. By significantly increasing yields, sometimes as much as 250 percent, Silicon Aware IP helps remove the barriers to the successful early adoption of advanced process technologies.
About Virage Logic
Founded in 1996, Virage Logic Corporation rapidly established itself as a technology and market leader in providing advanced embedded memory intellectual property (IP) for the design of complex integrated circuits. Today the company is a global leader in semiconductor IP platforms comprising embedded memories, standard cells, and I/Os and is pioneering the development of a new class of IP called Silicon Aware IP. Silicon Aware IP tightly integrates Physical IP (memory, logic and I/Os) with the embedded test, diagnostic, and repair capabilities of Infrastructure IP to help ensure manufacturability and optimized yield at the advanced process nodes. Virage Logic's highly differentiated product portfolio provides higher performance, lower power, higher density and optimal yield to foundries, integrated device manufacturers (IDMs) and fabless customers who develop products for the consumer, communications and networking, hand-held and portable, and computer and graphics markets. The company's comprehensive quality efforts are validated in its FirstPass-Silicon Characterization Lab, which helps ensure high quality, reliable IP across a wide range of foundries and process technologies. Headquartered in Fremont, California, Virage Logic has R&D, sales and support offices worldwide. For more information, visit www.viragelogic.com.
SAFE HARBOR STATEMENT FOR VIRAGE LOGIC UNDER THE PRIVATE SECURITIES LITIGATION REFORM ACT OF 1995:
Statements made in this news release, other than statements of historical fact, are forward-looking statements, including, for example, statements relating to trends, business outlook, products, and customer relationships. Forward-looking statements are subject to a number of known and unknown risks and uncertainties, which might cause actual results to differ materially from those expressed or implied by such statements. These risks and uncertainties include Virage Logic's ability to forecast its business, including its revenue, income and order flow outlook; Virage Logic's ability to execute on its strategy to become a provider of semiconductor IP platforms; Virage Logic's ability to continue to develop new products and maintain and develop new relationships with third-party foundries and integrated device manufacturers; adoption of Virage Logic's technologies by semiconductor companies and increases or fluctuations in the demand for their products; the company's ability to overcome the challenges associated with establishing licensing relationships with semiconductor companies; the company's ability to obtain royalty revenues from customers in addition to license fees, to receive accurate information necessary for calculating royalty revenues and to collect royalty revenues from customers; business and economic conditions generally and in the semiconductor industry in particular; competition in the market for semiconductor IP platforms; and other risks including those described in the company's Annual Report on Form 10-K for the period ended September 30, 2004, and in Virage Logic's other periodic reports filed with the SEC, all of which are available from Virage Logic's website ( www.viragelogic.com) or from the SEC's website ( www.sec.gov), and in news releases and other communications. Virage Logic disclaims any intention or duty to update any forward-looking statements made in this news release.
NOTE: All trademarks and copyrights are property of their respective owners and are protected therein.
CONTACT: Sabina Burns of Virage Logic Corporation, +1-510-743-8115, or
Email Contact; or Kerry McClenahan of McClenahan Bruer
Communications, +1-503-546-1002, or Email Contact, for Virage Logic
Web site: http://www.viragelogic.com/