Toshiba Supports Cadence Encounter RTL Compiler for ASIC Design Flow; Cadence Synthesis Enables Smooth Transition to Successful Tapeout
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Toshiba Supports Cadence Encounter RTL Compiler for ASIC Design Flow; Cadence Synthesis Enables Smooth Transition to Successful Tapeout

SAN JOSE, Calif.—(BUSINESS WIRE)—Dec. 13, 2004— Cadence Design Systems, Inc. (NYSE: CDN) (Nasdaq: CDN) today announced that Toshiba America Electronic Components, Inc. (TAEC) has introduced a design kit to support its Custom System-on-Chip (SoC) and application-specific integrated circuit (ASIC) customers using Cadence(R) Encounter(TM) RTL Compiler synthesis. The new kit supports designs for implementing in TC280 (130nm), TC300 (90nm) and newer process technologies. Customers now can use this smooth, qualified flow for RTL-to-netlist synthesis and netlist-to-netlist optimization with Encounter RTL Compiler.

"We have successfully used SoC Encounter for the past two years to take complex custom designs into production," said Shigenori Imazato, vice president of engineering for TAEC Design Centers. "These have mostly been at TC280 (130nm) technology level. By adopting Encounter RTL Compiler in addition to SoC Encounter, we have realized a consistent, streamlined flow from RTL-to-GDS. By using the Cadence SoC Encounter RTL-to-GDS flow, we can achieve better performance and faster turnaround time."

"TAEC has been a long-time user of Encounter RTL Compiler, beginning with its successful use on the world's fastest synthesizable 64-bit MIPs core in 2002," said Chi-Ping Hsu, corporate vice president, synthesis solutions, Cadence. "An increasing number of Custom SoC/ASIC vendors such as TAEC are selecting Encounter RTL Compiler as the final synthesis tool in their signoff flow because of its proven ability to increase chip performance, speed turnaround time and produce higher Quality of Silicon (QoS)."

QoS measures a design's physical characteristics using wires in terms of improved area utilization and higher performance. Optimizing QoS is important when designing advanced ASICs and is a significant factor in reducing time to market.

A critical step in the fastest route to superior silicon, Encounter RTL Compiler derives its advantages from its advanced logic structure creation algorithms. Unlike other synthesis tools that rely on dated, local and incremental optimization techniques, RTL Compiler applies a global approach that encompasses multi-objective, multi-level and multi-path techniques to help achieve higher QoS in less time.


The design kit supporting Encounter RTL Compiler will be available from TAEC by early January 2005.

About Cadence

Cadence is the world's largest supplier of electronic design technologies and engineering services. Cadence products and services are used to accelerate and manage the design of semiconductors, computer systems, networking equipment, telecommunications equipment, consumer electronics, and other electronics based products. With approximately 4,850 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and trades on both the New York Stock Exchange and Nasdaq under the symbol CDN. More information is available at

Cadence and the Cadence logo are registered trademarks and Encounter is a trademark of Cadence Design Systems, Inc. in the U.S. and other countries. All other trademarks are the property of their respective owners.

Cadence Design Systems, Inc.
Judy Erkanat, 408-894-2302

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