Cadence Introduces Industry's First Yield Diagnostics Tool; Encounter Test Pinpoints Most Critical Design-Related Yield Issues

SAN JOSE, Calif.—(BUSINESS WIRE)—Oct. 19, 2004— Cadence Design Systems, Inc. (NYSE: CDN) (Nasdaq: CDN) today announced Cadence(R) Encounter(TM) Diagnostics, the industry's first yield diagnostics tool. Encounter Diagnostics accelerates yield by identifying customers' most critical nanometer IC yield issues and precisely locating root cause defects. The result is higher yield in less time. The new tool supports all digital design styles and test vectors produced by all popular ATPG tools.

"Leading-edge chip designers and manufacturers require advanced diagnostic tools to effectively test and verify their increasingly complex designs," said Michael Bouvier, manager of PowerPC New Product Intro at IBM. "We collaborated with Cadence to refine a diagnostics system that can deliver a unique set of features and capabilities ideal for both volume and precision nanometer diagnostics."

Yield ramp is perhaps the biggest challenge presented by nanometer designs today. According to a recent report from International Business Strategies, Inc., the time to reach nominal yield has lengthened to six to nine months for 130-nanometer designs. Many IC products do not reach expected yields during their lifetime. The main problem is subtle design-process interactions that are not predictable before actual silicon and difficult to isolate within silicon.

Encounter Diagnostics brings a proven solution to the general market for the first time. Developed in conjunction with IBM and demonstrated with select customers, the tool provides a unique set of advanced capabilities required for effective volume and precision operation. It includes static and dynamic diagnostics, patented Pattern Fault Modeling, and support of all industry standard test vectors.

Traditional ATPG-based diagnostics tools are typically less than 40 percent accurate at 130 nanometers and do not support volume operation, dynamic diagnostics, customizable fault modeling, or vectors generated by other ATPG tools. Encounter Diagnostics was developed specifically to accelerate nanometer yield in production manufacturing environments. In volume mode, the tool identifies the most critical design-related issues based on analyzing a statistically significant sample size. In precision mode, it precisely locates the root cause defects, which can then be verified in a physical failure analysis lab.

"Combining Encounter Diagnostics' advanced precision capabilities with our EmiScope time-resolved emission microscope provides joint customers with a very effective method of locating nanometer defects," said Dr. Israel Niv, president, Diagnostics and Characterization Group, Credence Systems Corporation.

"AMD has used Encounter Diagnostics for evaluation and it has helped us achieve many of our target yields," said Pat Patla, director, Server/Workstation Marketing, AMD's Microprocessor Business Unit. "AMD is utilizing some of the most advanced software tools available within our Automated Precision Manufacturing to achieve unprecedented yield levels to deliver the greatest performance to our customers."

"Yield ramp is a huge problem for our customers working on nanometer ICs," said Paul Estrada, general manager of Encounter Test for Cadence Design Systems. "Encounter Diagnostics provides a proven system for quickly finding the root cause of the most critical design-related issues."

Encounter Diagnostics will be available in the Encounter Test 2.2 release shipping at the end of October.

About Cadence

Cadence is the world's largest supplier of electronic design technologies and engineering services. Cadence products and services are used to accelerate and manage the design of semiconductors, computer systems, networking equipment, telecommunications equipment, consumer electronics, and other electronics based products. With approximately 4,850 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and trades on both the New York Stock Exchange and Nasdaq under the symbol CDN. More information is available at

Cadence and the Cadence logo are registered trademarks and Encounter is a trademark of Cadence Design Systems, Inc. in the U.S. and other countries. All other trademarks are the property of their respective owners.

Cadence Design Systems, Inc.
Judy Erkanat, 408-894-2302

Email Contact

Review Article Be the first to review this article

Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
H-1B Visa: de Geus’ tragedy looms large
Peggy AycinenaIP Showcase
by Peggy Aycinena
IP for Cars: Lawsuits are like Sandstorms
More Editorial  
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Staff Software Engineer - (170059) for brocade at San Jose, CA
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Upcoming Events
Embedded Systems Conference ESC Boston 2017 at Boston Convention & Exhibition Center Boston MA - May 3 - 4, 2017
2017 GPU Tech Conference at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - May 8 - 11, 2017
High Speed Digital Design and PCB Layout at 13727 460 Ct SE North Bend WA - May 9 - 11, 2017
Nanotech 2017 Conference & Expo at Gaylord National Hotel & Convention Center WA - May 14 - 17, 2017

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy